View R5F52108ADFP11_3717066.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary datasheet specifications in this document are tentative and subject to change. r01ds0041ej0090 rev.0.90 page 1 of 144 aug 10, 2011 rx210 group renesas mcus features 32-bit rx cpu core ? max. operating frequency: 50 mhz capable of 78 dmips in operation at 50 mhz ? accumulator handles 64-bit results (for a single instruction) from 32- 32-bit operations ? multiplication and division unit handles 32- 32-bit operations (multiplication in structions take one cpu clock cycle) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instruc tions, ultra-compact code ? on-chip debugging circuit low-power design and architecture ? operation from a single 1.62- to 5.5-v supply ? 1.62-v operation available (at up to 20 mhz) ? deep software standby mode with rtc remaining usable ? four low-power modes on-chip flash memory for code, no wait states ? 50-mhz operation, 20-ns read cycle ? no wait states for reading at full cpu speed ? 128- to 512-kbyte capacities ? user code programmable via the sci ? programmable at 1.62 v ? for instructions and operands on-chip data flash memory ? eight kbytes ? erasing and programming impose no load on the cpu. on-chip sram, no wait states ? 20- to 64-kbyte size capacities dma ? dmaca: incorporates four channels ? dtc: four transfer modes elc ? module operation can be initiated by event signals without going through interrupts. ? modules can operate while the cpu is sleeping. reset and supply management ? nine types of reset, includi ng the power-on reset (por) ? low voltage detection (l vd) with voltage settings clock functions ? frequency of external clock: up to 20 mhz ? frequency of the oscillator for sub-clock generation: 32.768 khz ? pll circuit input: 4 to 12.5 mhz ? on-chip low- and high-speed oscillators, dedicated on- chip low-speed oscillator for the iwdt ? generation of a dedicated 32.768-khz clock for the rtc ? clock frequency accuracy me asurement circuit (cac) real-time clock ? adjustment fu nctions (3 0 sec onds, leap year, and error) ? time capture function ? time capture on event-signal input through external pins ? rtc capable of initiating re turn from deep software standby mode independent watchdog timer ? 125-khz on-chip low-speed oscillator produces a dedicated clock signal to drive iwdt operation. useful functions for iec60730 compliance ? self-diagnostic and disconnect ion-detection functions for the ad converter, clock-frequency accuracy- measurement circuit, inde pendent watchdog timer, functions to assist in ram testing, etc. up to nine communications interfaces ? sci with many useful functions (up to seven interfaces) ? asynchronous mode, clock synchronous mode, smart card interface ? i 2 c bus interface: transfer at up to 1 mbps, capable of smbus operation (1 interface) ? rspi (1) external address space ? four cs areas (4 16 mbytes) ? 8- or 16-bit bus space is selectable per area up to 14 extend ed-function timers ? 16-bit mtu2: input captur e, output capture, complementary pwm output, phase counting mode (6 channels) ? 8-bit tmr (4 channels) ? 16-bit compare-match timers (4 channels) 12-bit a/d converter ? capable of conversion within 1 s ? sample-and-hold circuits (for three channels) ? three-channel synchroni zed sampling available ? self-diagnostic function and analog input disconnection detection assist ance function 10-bit d/a converter analog comparator programmable i/o ports ? 5-v tolerant, open drain, input pull-up, switching of driving ability mpc ? multiple locations are selectable for i/o pins of peripheral functions temperature sensor operating temp. range ? -40 ?c to +85 ?c plqp0100kb-a 14 14 mm, 0.5-mm pitch plqp0080kb-a 12 12 mm, 0.5-mm pitch plqp0080ja-a 14 14 mm, 0.65-mm pitch plqp0064kb-a 10 10 mm, 0.5-mm pitch plqp0064ga-a 14 14 mm, 0.8-mm pitch ptlg0100ja-a 7 7 mm, 0.65-mm pitch 50-mhz 32-bit rx mcus, 78 dmips, up to 512-kb flash memory, 12-bit ad, 10-bit da, elc, mpc, rtc, up to 9 comms interfaces; incorporating functions for iec60730 compliance r01ds0041ej0090 rev.0.90 aug 10, 2011
r01ds0041ej0090 rev.0.90 page 2 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. 1. overview 1.1 outline of specifications table 1.1 lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different packages. table 1.1 is for products with the greatest number of functions , so numbers of peripheral modules and channels will differ in accord with the package. for details, see table 1.2, comparison of func tions for different packages . table 1.1 outline of specifications (1 / 3) classification module/function description cpu cpu ? maximum operating frequency: 50 mhz ? 32-bit rx cpu ? minimum instruction exec ution time: one instruction per st ate (cycle of the system clock) ? address space: 4-gbyte linear ? register set of the cpu general purpose: sixteen 32-bit registers control: eight 32-bit registers accumulator: one 64-bit register ? basic instructions: 73 ? dsp instructions: 9 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32 x 32 ? 64 bits ? on-chip divider: 32 / 32 ? 32 bits ? barrel shifter: 32 bits memory rom ? rom capacity: 512 kbytes (max.) ? three on-board programming modes boot mode (the user mat and the user boot mat are programmable via the sci.) user boot mode user program mode ? parallel programmer mode (for off-board programming) ram ram capacity: 64 kbytes (max.) e2 data flash e2 data flash capacity: 8 kbytes mcu operating mode single-chip mode, on-chip rom enabled expansion mode, and on-chip rom disabled expansion mode (software switching) clock clock generation circuit ? main clock oscillator, sub-clock oscillator, low-sp eed on-chip oscillator, high-speed on-chip oscillator, pll frequency synthesizer, and dedicated low-speed on-chip oscillator for iwdt ? oscillation stop detection ? measuring circuit for accurcy of cloc k frequency (clock-accurcy check: cac) ? independent frequency-division and mu ltiplication settings for the system clock (iclk), peripheral module clock (pclk), external bus clock (bclk), and flashif clock (fclk) the cpu and system sections such as other bus masters run in synchronization with the system clock (iclk): 50 mhz (at max.) peripheral modules run in synchronization with the peripheral module clock (pclk): 32 mhz (at max.) devices connected to the external bus run in synch ronization with the external bus clock (bclk): 12.5 mhz (at max.) the flash peripheral circuit runs in synchronization with the flash peripheral clock (fclk): 32 mhz (at max.) reset pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, deep software standby reset, and software reset voltage detection voltage detection circuit (lvd) ? when the voltage on vcc falls below the voltage detection level, an internal reset or internal interrupt is generated. voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels low power consumption low power consumption facilities ? module stop function ? four low power consumption modes sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode interrupt interrupt control unit (icu) ? interrupt vectors: 117 ? external interrupts: 9 (nmi and irq0 to irq7 pins) ? non-maskable interrupts: 6 (the nmi pin, oscillation stop detection interrupt, voltage-monitoring interrupt 1, voltage-monitoring interrupt 2, wdt interrupt, and iwdt interrupt) ? 16 levels specifiable for the order of priority
r01ds0041ej0090 rev.0.90 page 3 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. external bus extension ? the external address space can be divided into four areas (cs0 to cs3), each with independent control of access settings. capacity of each area: 16 mbytes (cs0 to cs3) a chip-select signal (cs0# to cs3#) can be output for each area. each area is specifiable as an 8- or 16-bit bus space the data arrangement in each area is selectable as little or big endian (only for data). bus format: separate bus, multiplex bus ? wait control ? write buffer facility dma dma controller (dmaca) ? 4 channels ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software trigger, external in terrupts, and interrupt requests from peripheral functions data transfer controller (dtc) ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: interrupts ? chain transfer function i/o ports programmable i/o ports 100-pin lqfp/80-pin lqfp/64-pin lqfp ? i/o pin: 84/64/48 ? input: 1/1/1 ? pull-up resistors: 85/65/49 ? open-drain outputs: 54/44/35 ? 5-v tolerance: 4/4/2 event link controller (elc) ? event signals of 59 types can be directly connected to the module ? operations of timer modules are selectable at event input ? capable of event link operation for ports b and e multifunction pin controller (mpc) ? capable of selecting input/output function from multiple pins timers multi-function timer pulse unit 2 (mtu2) ? (16 bits x 6 channels) x 1 unit ? time bases for the six 16-bit ti mer channels can be provided via up to 16 pulse-input/output lines and three pulse-input lines ? select from among eight or seven counter-input clock signals for each channel (pclk/1, pclk/4, pclk/16, pclk/64, pclk/256, pclk/1024, tclka, tclkb, tclkc, tclkd) other than channel 5, for which only four signals are available. ? input capture function ? 21 output compare/input capture registers ? pulse output mode ? complementary pwm output mode ? reset synchronous pwm mode ? phase-counting mode ? generation of triggers for a/d converter conversion port output enable2 (poe2) controls the high-impedance state of the mtu2?s waveform output pins from multiple pins 8-bit timer (tmr) ? (8 bits x 2 channels) x 2 units ? select from among seven internal clock signals (pclk, pclk/2, pclk/8, pclk/32, pclk/64, pclk/1024, pclk/8192) and one external clock signal ? capable of output of pulse trains wi th desired duty cycles or of pwm signals ? the 2 channels of each unit can be cascaded to create a 16-bit timer ? capable of generating baud-rate clocks for sci5, sci6, and sci12 compare match timer (cmt) ? (16 bits x 2 channels) x 2 units ? sel ect from among four clock signals (pclk/8, pclk/32, pclk/128, pclk/512) w atchdog timer (wdt) ? 14 bits x 1 channel ? select from among 6 counter-input clock signals (pclk/4, pclk/64, pclk/128, pclk/512, pclk/2048, pclk/8192) independent watchdog timer (iwdt) ? 14 bits x 1 channel ? counter-input clock: dedicated low-speed on-chip oscillator for iwdt frequency divided by 1, 16, 32, 64, 128, or 256 realtime clock (rtc) ? clock source: subclock ? time/calendar ? interrupt sources: alarm interrupt, periodic interrupt, and carry interrupt ? time-capture facility for three values table 1.1 outline of specifications (2 / 3) classification module/function description
r01ds0041ej0090 rev.0.90 page 4 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. communication function serial communications interfaces (scic, scid) ? 7 channels (channel 0, 1, 5, 6, 8, 9: scic, channel 12: scid) ? serial communications modes: asynchronous, clock synchronous, and smart-card interface ? on-chip baud rate generator allows selection of the desired bit rate ? choice of lsb-first or msb-first transfer ? average transfer rate clock can be input fr om tmr timers (scl5, scl6, and scl12) ? simple iic ? simple spi ? master/slave mode supported (scid only) ? start frame and information frame are included (scid only) i 2 c bus interface (riic) ? 1 channel ? communications formats: i 2 c bus format/smbus format ? master/slave selectable ? supports the first mode serial peripheral interface (rspi) ? 1 channel ? rspi transfer facility using the mosi (master out, slave in), miso (mast er in, slave out), ssl (slave select), and rspi clock (rspck) signals enables serial transfer through spi operation (four lines) or clock- synchronous operation (three lines) ? capable of handling serial transfer as a master or slave ? data formats ? choice of lsb-first or msb-first transfer the number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or receiv ed in a single transfer operation (with each frame having up to 32 bits) ? double buffers for both transmission and reception 12-bit a/d converter ? 12 bits (16 channels x 1 unit) ? 12-bit resolution ? conversion time: 1.0 ? s per channel (in operation with adclk at 50 mhz) ? operating modes scan mode (single-cycle scan mode, continuous scan mode, and group scan mode) ? sample-and-hold function ? self-diagnosis for the a/d converter ? assistance in detecting disconnected analog inputs ? double-trigger mode (duplexing of a/d-converted data) ? a/d conversion start conditions conversion can be started by software, a conversi on start trigger from a timer (mtu2), an external trigger signal, or elc. temperature sensor ? outputs the voltage that changes depending on the temperature ? pga gain switchable: four levels according to the voltage range d/a converter ? 2 channels ? 10-bit resolution ? output voltage: 0 v to vrefh crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb-firs t or msb-first communications is selectable. comparator a ? 2 channels ? comparison of reference voltage and analog input voltage comparator b ? 2 channels ? comparison of reference voltage and analog input voltage power supply voltage/ operating frequency vcc = 1.62 to 1.8 v: 20 mhz, vcc = 1.8 to 2.7 v: 32 mhz, vcc = 2.7 to 5.5 v: 50 mhz supply current tbd ma (typ.) operating temperature ? 40 to +85 ? c package 100-pin tflga (ptlg0100ja-a) 100-pin lqfp (plqp0100kb-a) 80-pin lqfp (plqp0080kb-a) 80-pin lqfp (plqp0080ja-a) 64-pin lqfp (plqp0064kb-a) 64-pin lqfp (plqp0064ga-a) table 1.1 outline of specifications (3 / 3) classification module/function description
r01ds0041ej0090 rev.0.90 page 5 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. table 1.2 comparison of functions for different packages module/functions rx210 group 100 pins 80 pins 64 pins external bus cs areas: 4 (cs0 to cs3) supported not supported not supported interrupt external interrupts nmi, irq0 to irq7 dma dma controller (dmac) 4 channels (dmac0 to dmac3) data transfer controller (dtc) supported timers multi-function timer pulse unit 2 (mtu2) 6 channels (mtu0 to mtu5) port output enable 2 (poe2) poe0# to poe3#, poe8# 8-bit timer (tmr) 2 channels 2 units compare match timer (cmt) 2 channels 2 units realtime clock (rtc) supported watchdog timer (wdt) supported independent watchdog timer (iwdt) supported communication function serial communications interface (scic) 6 channels (sci0, 1, 5, 6, 8, 9) 5 channels (sci1, 5, 6, 8, 9) serial communications inte rface (scid) 1 channel (sci12) i 2 c bus interface (riic) 1 channel serial peripheral interface (rspi) 1 channel 12-bit a/d converter 16 channels (an000 to an015) 14 channels (an000 to an013) 12 channels (an000 to an004, an006, an008 to an013) temperature sensor supported d/a converter 2 channels crc calculator (crc) supported event link controller (elc) supported comparator a 2 channels comparator b 2 channels package 100-pin tflga 100-pin lqfp 80-pin lqfp 64-pin lqfp
r01ds0041ej0090 rev.0.90 page 6 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. 1.2 list of products table 1.3 is a list of products, and figure 1.1 shows how to read the product pa rt no., memory capacity, and package type. table 1.3 list of products group part no. package rom capacity ram capacity e2 data flash operating frequency (max.) rx210 r5f52108adfp plqp0100kb-a 512 kbytes 64 kbytes 8 kbytes 50 mhz r5f52108adfg t.b.d 512 kbytes r5f52108adfn plqp0080kb-a 512 kbytes r5f52108adff plqp0080ja-a 512 kbytes r5f52108adfm plqp0064kb-a 512 kbytes r5f52108adfk plqp0064ga-a 512 kbytes r5f52108adlj ptlg0100ja-a 512 kbytes r5f52107adfp plqp0100kb-a 384 kbytes r5f52107adfg t.b.d 384 kbytes r5f52107adfn plqp0080kb-a 384 kbytes r5f52107adff plqp0080ja-a 384 kbytes r5f52107adfm plqp0064kb-a 384 kbytes r5f52107adfk plqp0064ga-a 384 kbytes r5f52107adlj ptlg0100ja-a 384 kbytes r5f52106adfp plqp0100kb-a 256 kbytes 32 kbytes r5f52106adfg t.b.d 256 kbytes r5f52106adfn plqp0080kb-a 256 kbytes r5f52106adff plqp0080ja-a 256 kbytes r5f52106adfm plqp0064kb-a 256 kbytes r5f52106adfk plqp0064ga-a 256 kbytes r5f52106adlj ptlg0100ja-a 256 kbytes r5f52105adfp plqp0100kb-a 128 kbytes 20 kbytes r5f52105adfg t.b.d 128 kbytes r5f52105adfn plqp0080kb-a 128 kbytes r5f52105adff plqp0080ja-a 128 kbytes r5f52105adfm plqp0064kb-a 128 kbytes r5f52105adfk plqp0064ga-a 128 kbytes r5f52105adlj ptlg0100ja-a 128 kbytes
r01ds0041ej0090 rev.0.90 page 7 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. figure 1.1 how to read the product part no., memory capacity, and package type type of memory f: flash memory version package type, number of pins, and pin pitch fp : lqfp/100/0.50 fn : lqfp/80/0.50 fm : lqfp/64/0.50 fg : lqfp/100/0.65 ff : lqfp/80/0.65 fk : lqfp/64/0.80 lj : tflga/100/0.65 rom, ram, and e2 data flash capacity 8: 512 kbytes/64 kbytes/8 kbytes 7: 384 kbytes/64 kbytes/8 kbytes 6: 256 kbytes/32 kbytes/8 kbytes 5: 128 kbytes/20 kbytes/8 kbytes group name 10 : rx210 group renesas mcu renesas semicond uctor product series name rx200 series r 5 f 5 2 d f p a801 d : products with wide temperature-range spec. (-40 to +85c)
r01ds0041ej0090 rev.0.90 page 8 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram external bus bsc icu: interrupt control unit dtc: data transfer controller dmaca: dma controller bsc: bus controller wdt: watchdog timer iwdt: independent watchdog timer elc: event link controller crc: crc (cyclic redundancy check) calculator sci: serial communications interface rspi: serial peripheral interface riic: i 2 c bus interface mtu2: multi-function timer pulse unit 2 poe2: port output enable 2 tmr: 8-bit timer cmt: compare match timer rtc: realtime clock doc: data operation circuit cac: clock-frequency accu racy measuring circuit operand bus instruction bus internal main bus 1 clock generation circuit rx cpu ram rom port 0 port 1 port 2 port 3 port 4 10-bit d/a converter 2 channels temperature sensor riic 1 channel doc scic 6 channels wdt e2 data flash crc elc rtc mtu2 6 channels 12-bit a/d converter 16 channels cmt x 2 channels (unit 1) cmt x 2 channels (unit 0) tmr x 2 channels (unit 1) tmr 2 channels (unit 0) rspi 1 channel internal peripheral buses 1 to 6 internal main bus 2 dtc dmaca 4 channels icu cac scid 1 channel port 5 port a port b port c port d port e port h port j poe2 iwdt comparator b 2 channels comparator a 2 channels
r01ds0041ej0090 rev.0.90 page 9 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1 / 4) classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl input connect this pin to vss via a 0.1 ? f capacitor. the capacitor should be placed close to the pin. vss input ground pin. connect it to the system power supply (0 v). clock xtal output pins for connecting a crystal resonator. an external clock signal can be input through the extal pin. extal input bclk output outputs the external bus clock for external devices. xcin input input/output pins for the subclock generation circuit. connect a crystal resonator between xcin and xcout. xcout output operating mode control md input pins for setting the operating m ode. the signal levels on this pin must not be changed during operation. system control res# input reset signal input pin. this lsi enters the reset state when this signal goes low. cac cacref input input pin for the measuri ng circuit for cloc k frequency precision. on-chip emulator fined i/o fine interface pin. finec input clock pin for fine interface. address bus a0 to a23 output output pins for the address. data bus d0 to d15 i/o input and output pins for the bidirectional data bus. bus control rd# output strobe signal which indi cates that reading from the external bus interface space is in progress. wr# output strobe signal which indicates that writing to the external bus interface space is in progress, in single-write strobe mode. wr0#, wr1# output strobe signals which indicate that either group of data bus pins (d7 to d0, and d15 to d8) is valid in writing to the external bus interface space, in byte strobe mode. bc0#, bc1# output strobe signals which indicate that either group of data bus pins (d7 to d0 and d15 to d8) is valid in access to the external bus interface space, in single-write strobe mode. cs0# to cs3# output select signals for areas 0 to 3. wait# input input pins for wait request signals in access to the external space. ale output address latch signal when address/data multiplexed bus is selected. interrupt (icu) nmi input non-maskable interrupt request signal. irq0 to irq7 input interrupt request signals.
r01ds0041ej0090 rev.0.90 page 10 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. multi-function timer pulse unit 2 (mtu2) mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/ pwm output pins. mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/ pwm output pins. mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/ pwm output pins. mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/ pwm output pins. mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/ pwm output pins. mtic5u, mtic5v, mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/external pulse input pins. mtclka, mtclkb, mtclkc, mtclkd input input pins for external clock signals. port output enable 2 (poe2) poe0# to poe3#, poe8# input input pins for reques t signals to place the mtu2 pins in the high impedance state. 8-bit timer (tmr) tmo0 to tmo3 output compare match output pins. tmci0 to tmci3 input input pins for external clocks to be input to the counter. tmri0 to tmri3 input input pins for the counter reset. realtime clock (rtc) rtcout output output pin for 1-hz clock. rtcic0 to rtcic2 input tamper resistant event input pins. serial communications interface (scic) ? asynchronous mode/clock synchronous mode sck0, sck1, sck5, sck6, sck8, sck9 i/o input/output pins for clock signals rxd0, rxd1, rxd5, rxd6, rxd8, rxd9 input input pins for received data txd0, txd1, txd5, txd6, txd8, txd9 output output pins for transmitted data cts0#, cts1#, cts5#, cts6#, cts8#, cts9# input input pins for controlling the start of transmission and reception rts0#, rts1#, rts5#, rts6#, rts8#, rts9# output output pins for controlling th e start of transmission and reception ? simple i 2 c mode sscl0, sscl1, sscl5, sscl6, sscl8, sscl9 i/o input/output pins for the i 2 c clock ssda0, ssda1, ssda5, ssda6, ssda8, ssda9 i/o input/output pins for the i 2 c data ? simple spi mode sck0, sck1, sck5, sck6, sck8, sck9 i/o input/output pins for the clock smiso0, smiso1, smiso5, smiso6, smiso8, smiso9 i/o input/output pins for slave transmission of data smosi0, smosi1, smosi5, smosi6, smosi8, smosi9 i/o input/output pins for master transmission of data ss0# to ss11# input chip-select input pins table 1.4 pin functions (2 / 4) classifications pin name i/o description
r01ds0041ej0090 rev.0.90 page 11 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. serial communications interface (scid) ? asynchronous mode/clock synchronous mode sck12 i/o input/output pin for the clock signal rxd12 input input pin for received data txd12 output output pin for transmitted data cts12# input input pin for controlling t he start of transmission and reception rts12# output output pin for controlling the start of transmission and reception ? simple i 2 c mode sscl12 i/o input/output pin for the i 2 c clock ssda12 i/o input/output pin for the i 2 c data ? simple spi mode sck12 i/o input/output pin for the clock smiso12 i/o input/output pin for slave transmit data smosi12 i/o input/output pin for master transmit data ss12# input chip-select input pin ? extended serial mode rxdx12 input input pin for data reception by scid txdx12 output output pin for data transmission by scid siox12 i/o input/output pin for data reception or transmission by scid i 2 c bus interface (riic) scl i/o input/output pin for i 2 c bus interface clocks . bus can be directly driven by the nmos open drain output. sda i/o input/output pin for i 2 c bus interface data. bus can be directly driven by the nmos open drain output. serial peripheral interface (rspi) rspcka i/o clock input/output pin for the rspi. mosia i/o input or output data output from the master for the rspi. misoa i/o input or output data output from the slave for the rspi. ssla0 i/o input/output pin to select the slave for the rspi. ssla1 to ssla3 output output pins to select the slave for the rspi. 12-bit a/d converter an000 to an015 input input pin for the analog signals to be processed by the a/d converter. adtrg0# input input pin for the external trigger signals that start the a/d conversion. d/a converter da0, da1 output output pins for t he analog signals to be processed by the d/a converter. comparator a cmpa1 input input pin fo r the comparator a1 analog signals. cmpa2 input input pin for the comparator a2 analog signals. cvrefa input input pin for the comparator reference voltage. comparator b cmpb0 input input pin for the comparator b0 analog signals. cvrefb0 input input pin for the comparator b0 reference voltage. cmpb1 input input pin for the comparator b1 analog signals. cvrefb1 input input pin for the comparator b1 reference voltage. table 1.4 pin functions (3 / 4) classifications pin name i/o description
r01ds0041ej0090 rev.0.90 page 12 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. analog power supply avcc0 input analog voltage supply pin for t he 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used. avss0 input analog ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used. vrefh0 input analog reference voltage supply pin for the 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used. vrefl0 input analog reference ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used. vrefh input analog voltage supply pin for the d/a converter. connect this pin to vcc if the d/a converter is not to be used. vrefl input analog ground pin for the d/a converter. connect this pin to vss if the d/a converter is not to be used. i/o ports p03, p05, p07 i/o 3-bit input/output pins. p12 to p17 i/o 6-bit input/output pins. p20 to p27 i/o 8-bit input/output pins. p30 to p37 i/o 8-bit input/output pins. (p35 input pins) p40 to p47 i/o 8-bit input/output pins. p50 to p55 i/o 6-bit input/output pins. pa0 to pa7 i/o 8-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pc0 to pc7 i/o 8-bit input/output pins. pd0 to pd7 i/o 8-bit input/output pins. pe0 to pe7 i/o 8-bit input/output pins. ph0 to ph3 i/o 4-bit input/output pins. pj1, pj3 i/o 2-bit input/output pins. table 1.4 pin functions (4 / 4) classifications pin name i/o description
r01ds0041ej0090 rev.0.90 page 13 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. 1.5 pin assignments figure 1.4 to figure 1.6 show the pin assignments. table 1.5 to table 1.8 show the lists of pins and pin functions. figure 1.3 pin assignments of the 100-pin tflga (upper perspective view) pe2 rx210 group ptlg0100ja-a (100-pin tflga) (upper perspective view) note: ? this figure indicates the power supply pi ns and i/o port pins. for the pin configur ation, see the table ?list of pins and pin functions (100-pin tflga)?. ? for the position of a1 pin in t he package, see ?pa ckage dimensions?. pe1 pe0 pd4 pd0 p43 vrefl0 p07 vrefh p05 pe3 pd7 pd6 pd3 pd1 p44 p40 avcc0 avss0 p03 pe4 pe5 pd5 pd2 p47 p42 vrefh0 pj3 vrefl vcl pa0 pa1 pe7 pe6 p46 p45 pj1 md xcout xcin pa3 pa5 pa4 pa6 pa2 p41 p34 res# vss p37/ xtal vss pa7 pb0 pb2 pb3 p12 p32 p35 vcc p36/ extal vcc pb1 pb4 pb5 p52 p53 p27 p30 p31 p33 pb7 pb6 pc6 pc7 p54 p55 p15 p16 p25 p26 p17 pc1 pc0 pc4 p50 ph3 ph0 p13 p21 p24 pc2 pc3 pc5 p51 ph1 ph2 p14 p20 p22 p23 k j h g f e d c b a 10987654321 k j h g f e d c b a 10987654321
r01ds0041ej0090 rev.0.90 page 14 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. figure 1.4 pin assignments of the 100-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pe0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 p47 p46 p45 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p07 avss0 pe1 p44 pc2 pc4 pc5 pc6 pc7 p50 p51 p52 p53 p54 p55 ph0 ph1 ph3 p12 p13 p14 p15 p16 p17 p20 p21 p22 pc3 ph2 pe3 pe5 pe6 pe7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vss vcc pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pe4 pb0 vrefh vrefl pj3 vcl pj1 md xcin xcout res# p37/xtal vss p36/exta l p35 p34 p33 p32 p31 p30 p27 p26 p25 p23 p03 vcc pe2 p05 p24 rx210 group plqp0100kb-a (100-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (100-pin lqfp)?.
r01ds0041ej0090 rev.0.90 page 15 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. figure 1.5 pin assignments of the 80-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 pe2 pe1 pe0 pd2 pd1 pd0 p47 p46 p45 p44 p43 p42 vrefl0 p40 vrefh0 avcc0 p07 avss0 p05 p41 pc2 pc4 pc5 pc6 pc7 p54 p55 ph0 ph1 ph2 ph3 p12 p13 p15 p16 p17 p20 p21 pc3 p14 pe3 pe4 pe5 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pb0 vcc pb1 pb2 pb3 pb4 pb5 pb6 pb7 vss vrefh vrefl vcl pj1 md xcin xcout res# p37/xtal vss p36/extal vcc p34 p32 p31 p30 p27 p26 p03 p35 rx210 group plqp0080kb-a (80-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (80-pin lqfp)?.
r01ds0041ej0090 rev.0.90 page 16 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. figure 1.6 pin assignments of the 64-pin lqfp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx210 group plqp0064kb-a (64-pin lqfp) (top view) pe2 pe1 pe0 vrefl p46 vrefh p44 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p05 avss0 pe3 pe4 pe5 pa0 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pb6 pb7 pc2 pc3 pc4 pc5 pc6 pc7 p54 p55 ph0 ph1 ph2 ph3 p14 p15 p16 p17 p03 vcl md xcin xcout res# p37/xtal vss p36/extal vcc p35 p32 p31 p30 p27 p26 note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin function s (64-pin lqfp)?.
r01ds0041ej0090 rev.0.90 page 17 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. table 1.5 list of pins and pin functions (100-pin tflga) (1 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu2, tmr, poe2) communications (scic, scid, rspi, riic) others a1 p05 da1 a2 vrefh a3 p07 adtrg0# a4 vrefl0 a5 p43 an003 a6 pd0 d0[a0/d0] irq0 a7 pd4 d4[a4/d4] poe3# irq4 a8 pe0 d8[a8/d8] sck12 an008 a9 pe1 d9[a9/d9] mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 a10 pe2 d10[a10/d10] mtioc4a rxd12/rxdx12/ smiso12/sscl12 irq7-ds/an010/ cvrefb0 b1 p03 da0 b2 avss0 b3 avcc0 b4 p40 an000 b5 p44 an004 b6 pd1 d1[a1/d1] mtioc4b irq1 b7 pd3 d3[a3/d3] poe8# irq3 b8 pd6 d6[a6/d6] mtic5v/poe1# irq6 b9 pd7 d7[a7/d7] mtic5u/poe0# irq7 b10 pe3 d11[a11/d11] mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 c1 vcl c2 vrefl c3 pj3 mtioc3c cts6#/rts6#/ss6# c4 vrefh0 c5 p42 an002 c6 p47 an007 c7 pd2 d2[a2/d2] mtioc4d irq2 c8 pd5 d5[a5/d5] mtic5w/poe2# irq5 c9 pe5 d13[a13/d13] mtioc4c/mtioc2b irq5/an013 c10 pe4 d12[a12/d12] mtioc4d/mtioc1a an012/cmpa2 d1 xcin d2 xcout d3 md fined d4 pj1 mtioc3a d5 p45 an005 d6 p46 an006 d7 pe6 d14[a14/d14] irq6/an014 d8 pe7 d15[a15/d15] irq7/an015 d9 pa1 a1 mtioc0b/mtclkc sck5/ssla2 cvrefa d10 pa0 a0/bc0# mtioc4a ssla1 cacref e1 xtal p37 e2 vss e3 res# e4 p34 mtioc0a/tmci3/ poe2# sck6 irq4 e5 p41 an001 e6 pa2 a2 rxd5/smiso5/sscl5/ ssla3
r01ds0041ej0090 rev.0.90 page 18 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. e7 pa6 a6 mtic5v/mtclkb/ tmci3/poe2# cts5#/rts5#/ss5#/ mosia e8 pa4 a4 mtic5u/mtclka/ tmri0 txd5/smosi5/ssda5/ ssla0 irq5-ds/cvrefb1 e9 pa5 a5 rspcka e10 pa3 a3 mtioc0d/mtclkd rxd5/smiso5/sscl5 irq6-ds/cmpb1 f1 extal p36 f2 vcc f3 p35 nmi f4 p32 mtioc0c/tmo3 txd6/smos i6/ssda6 irq2-ds/rtcout/ rtcic2 f5 p12 tmci1 scl irq2 f6 pb3 a11 mtioc0a/mtioc4a/ tmo0/poe3# sck6 f7 pb2 a10 cts6#/rts6#/ss6# f8 pb0 a8 mtic5w rxd6/smiso6/sscl6/ rspcka f9 pa7 a7 misoa f10 vss g1 p33 mtioc0d/tmri3/ poe3# rxd6/smiso6/sscl6 irq3-ds g2 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 g3 p30 mtioc4b/tmri3/ poe8# rxd1/smiso1/sscl1 irq0-ds/rtcic0 g4 p27 cs3# mtioc2b/tmci3 sck1 finec g5 bclk p53 g6 p52 rd# g7 pb5 a13 mtioc2a/mtioc1b/ tmri1/poe1# sck9 g8 pb4 a12 cts9#/rts9#/ss9# g9 pb1 a9 mtioc0c/mtioc4c/ tmci0 txd6/smosi6/ssda6 irq4-ds g10 vcc h1 p26 cs2# mtioc2a/tmo1 txd1/smosi1/ssda1 h2 p25 cs1# mtioc4c/mtclkb adtrg0# h3 p16 mtioc3c/mtioc3d/ tmo2 txd1/smosi1/ssda1/ mosia/scl-ds irq6/rtcout/ adtrg0# h4 p15 mtioc0b/mtclkb/ tmci2 rxd1/smiso1/sscl1 irq5 h5 p55 wait# mtioc4d/tmo3 h6 p54 ale mtioc4b/tmci1 h7 pc7 a23/cs0# mtioc3a/tmo2/ mtclkb txd8/smosi8/ssda8/ misoa cacref h8 pc6 a22/cs1# mtioc3c/mtclka/ tmci2 rxd8/smiso8/sscl8/ mosia h9 pb6 a14 mtioc3d rxd9/smiso9/sscl9 h10 pb7 a15 mtioc3b txd9/smosi9/ssda9 j1 p24 cs0# mtioc4a/mtclka/ tmri1 j2 p21 mtioc1b/tmci0 rxd0/smiso0/sscl0 j3 p17 mtioc3a/mtioc3b/ tmo1/poe8# sck1/misoa/ sda-ds irq7 j4 p13 mtioc0b/tmo3 sda irq3 j5 ph0 cacref table 1.5 list of pins and pin functions (100-pin tflga) (2 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu2, tmr, poe2) communications (scic, scid, rspi, riic) others
r01ds0041ej0090 rev.0.90 page 19 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. j6 ph3 tmci0 j7 p50 wr0#/wr# j8 pc4 a20/cs3# mtioc3d/mtclkc/ tmci1/poe0# sck5/cts8#/rts8#/ ss8#/ssla0 j9 pc0 a16 mtioc3c cts5#/rts5#/ss5#/ ssla1 j10 pc1 a17 mtioc3a sck5/ssla2 k1 p23 mtioc3d/mtclkd cts0#/rts0#/ss0# k2 p22 mtioc3b/mtclkc/ tmo0 sck0 k3 p20 mtioc1a/tmri0 txd0/smosi0/ssda0 k4 p14 mtioc3a/mtclka/ tmri2 cts1#/rts1#/ss1# irq4 k5 ph2 tmri0 irq1 k6 ph1 tmo0 irq0 k7 p51 wr1#/bc1#/wait# k8 pc5 a21/cs2#/wait# mtioc3b/mtclkd/ tmri2 sck8/rspcka k9 pc3 a19 mtioc4d txd5/smosi5/ssda5 k10 pc2 a18 mtioc4b rxd5/smiso5/sscl5/ ssla3 table 1.5 list of pins and pin functions (100-pin tflga) (3 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu2, tmr, poe2) communications (scic, scid, rspi, riic) others
r01ds0041ej0090 rev.0.90 page 20 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. table 1.6 list of pins and pin functions (100-pin lqfp) (1 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu2, tmr, poe2) communications (scic, scid, rspi, riic) others 1vrefh 2p03 da0 3vrefl 4 pj3 mtioc3c cts6#/rts6#/ss6# 5vcl 6pj1 mtioc3a 7md fined 8xcin 9 xcout 10 res# 11 xtal p37 12 vss 13 extal p36 14 vcc 15 p35 nmi 16 p34 mtioc0a/tmci3/ poe2# sck6 irq4 17 p33 mtioc0d/tmri3/ poe3# rxd6/smiso6/sscl6 irq3-ds 18 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 irq2-ds/rtcout/ rtcic2 19 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 20 p30 mtioc4b/tmri3/ poe8# rxd1/smiso1/sscl1 irq0-ds/rtcic0 21 p27 cs3# mtioc2b/tmci3 sck1 finec 22 p26 cs2# mtioc2a/tmo1 txd1/smosi1/ssda1 23 p25 cs1# mtioc4c/mtclkb adtrg0# 24 p24 cs0# mtioc4a/mtclka/ tmri1 25 p23 mtioc3d/mtclkd cts0#/rts0#/ss0# 26 p22 mtioc3b/mtclkc/ tmo0 sck0 27 p21 mtioc1b/tmci0 rxd0/smiso0/sscl0 28 p20 mtioc1a/tmri0 txd0/smosi0/ssda0 29 p17 mtioc3a/mtioc3b/ tmo1/poe8# sck1/misoa/ sda-ds irq7 30 p16 mtioc3c/mtioc3d/ tmo2 txd1/smosi1/ssda1/ mosia/scl-ds irq6/rtcout/ adtrg0# 31 p15 mtioc0b/mtclkb/ tmci2 rxd1/smiso1/sscl1 irq5 32 p14 mtioc3a/mtclka/ tmri2 cts1#/rts1#/ss1# irq4 33 p13 mtioc0b/tmo3 sda irq3 34 p12 tmci1 scl irq2 35 ph3 tmci0 36 ph2 tmri0 irq1 37 ph1 tmo0 irq0 38 ph0 cacref 39 p55 wait# mtioc4d/tmo3 40 p54 ale mtioc4b/tmci1 41 bclk p53 42 p52 rd#
r01ds0041ej0090 rev.0.90 page 21 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. 43 p51 wr1#/bc1#/wait# 44 p50 wr0#/wr# 45 pc7 a23/cs0# mtioc3a/tmo2/ mtclkb txd8/smosi8/ssda8/ misoa cacref 46 pc6 a22/cs1# mtioc3c/mtclka/ tmci2 rxd8/smiso8/sscl8/ mosia 47 pc5 a21/cs2#/wait# mtioc3b/mtclkd/ tmri2 sck8/rspcka 48 pc4 a20/cs3# mtioc3d/mtclkc/ tmci1/poe0# sck5/cts8#/rts8#/ ss8#/ssla0 49 pc3 a19 mtioc4d txd5/smosi5/ssda5 50 pc2 a18 mtioc4b rxd5/smiso5/sscl5/ ssla3 51 pc1 a17 mtioc3a sck5/ssla2 52 pc0 a16 mtioc3c cts5#/rts5#/ss5#/ ssla1 53 pb7 a15 mtioc3b txd9/smosi9/ssda9 54 pb6 a14 mtioc3d rxd9/smiso9/sscl9 55 pb5 a13 mtioc2a/mtioc1b/ tmri1/poe1# sck9 56 pb4 a12 cts9#/rts9#/ss9# 57 pb3 a11 mtioc0a/mtioc4a/ tmo0/poe3# sck6 58 pb2 a10 cts6#/rts6#/ss6# 59 pb1 a9 mtioc0c/mtioc4c/ tmci0 txd6/smosi6/ssda6 irq4-ds 60 vcc 61 pb0 a8 mtic5w rxd6/smiso6/sscl6/ rspcka 62 vss 63 pa7 a7 misoa 64 pa6 a6 mtic5v/mtclkb/ tmci3/poe2# cts5#/rts5#/ss5#/ mosia 65 pa5 a5 rspcka 66 pa4 a4 mtic5u/mtclka/ tmri0 txd5/smosi5/ssda5/ ssla0 irq5-ds/cvrefb1 67 pa3 a3 mtioc0d/mtclkd rxd5/ smiso5/sscl5 irq6-ds/cmpb1 68 pa2 a2 rxd5/smiso5/sscl5/ ssla3 69 pa1 a1 mtioc0b/mtclkc sck5/ssla2 cvrefa 70 pa0 a0/bc0# mtioc4a ssla1 cacref 71 pe7 d15[a15/d15] irq7/an015 72 pe6 d14[a14/d14] irq6/an014 73 pe5 d13[a13/d13] mtioc4c/mtioc2b irq5/an013 74 pe4 d12[a12/d12] mtioc4d/mtioc1a an012/cmpa2 75 pe3 d11[a11/d11] mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 76 pe2 d10[a10/d10] mtioc4a rxd12/rxdx12/ smiso12/sscl12 irq7-ds/an010/ cvrefb0 77 pe1 d9[a9/d9] mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 78 pe0 d8[a8/d8] sck12 an008 79 pd7 d7[a7/d7] mtic5u/poe0# irq7 80 pd6 d6[a6/d6] mtic5v/poe1# irq6 81 pd5 d5[a5/d5] mtic5w/poe2# irq5 table 1.6 list of pins and pin functions (100-pin lqfp) (2 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu2, tmr, poe2) communications (scic, scid, rspi, riic) others
r01ds0041ej0090 rev.0.90 page 22 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. 82 pd4 d4[a4/d4] poe3# irq4 83 pd3 d3[a3/d3] poe8# irq3 84 pd2 d2[a2/d2] mtioc4d irq2 85 pd1 d1[a1/d1] mtioc4b irq1 86 pd0 d0[a0/d0] irq0 87 p47 an007 88 p46 an006 89 p45 an005 90 p44 an004 91 p43 an003 92 p42 an002 93 p41 an001 94 vrefl0 95 p40 an000 96 vrefh0 97 avcc0 98 p07 adtrg0# 99 avss0 100 p05 da1 table 1.6 list of pins and pin functions (100-pin lqfp) (3 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu2, tmr, poe2) communications (scic, scid, rspi, riic) others
r01ds0041ej0090 rev.0.90 page 23 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. table 1.7 list of pins and pin functions (80-pin lqfp) (1 / 2) pin no. power supply, clock, system control i/o port timers (mtu2, tmr, poe2) communications (scic, scid, rspi, riic) others 1vrefh 2p03 da0 3vrefl 4vcl 5pj1mtioc3a 6md fined 7xcin 8 xcout 9res# 10 xtal p37 11 vss 12 extal p36 13 vcc 14 p35 nmi 15 p34 mtioc0a/tmci3/poe2# sck6 irq4 16 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 irq2-ds/rtcout/ rtcic2 17 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 18 p30 mtioc4b/tmri3/poe8# rxd1 /smiso1/sscl1 irq0-ds/rtcic0 19 p27 mtioc2b/tmci3 sck1 finec 20 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 21 p21 mtioc1b/tmci0 rxd0/smiso0/sscl0 22 p20 mtioc1a/tmri0 txd0/smosi0/ssda0 23 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/ sda-ds irq7 24 p16 mtioc3c/mtioc3d/tmo2 t xd1/smosi1/ssda1/mosia/ scl-ds irq6/rtcout/ adtrg0# 25 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 irq5 26 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 27 p13 mtioc0b/tmo3 sda irq3 28 p12 tmci1 scl irq2 29 ph3 tmci0 30 ph2 tmri0 irq1 31 ph1 tmo0 irq0 32 ph0 cacref 33 p55 mtioc4d/tmo3 34 p54 mtioc4b/tmci1 35 pc7 mtioc3a/tmo2/mtclkb txd8 /smosi8/ssda8/misoa cacref 36 pc6 mtioc3c/mtclka/tmci 2 rxd8/smiso8/sscl8/mosia 37 pc5 mtioc3b/mtclkd/tmri2 sck8/rspcka 38 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 39 pc3 mtioc4d txd5/smosi5/ssda5 40 pc2 mtioc4b rxd5/smiso5/sscl5/ssla3 41 pb7 mtioc3b txd9/smosi9/ssda9 42 pb6 mtioc3d rxd9/smiso9/sscl9 43 pb5 mtioc2a/mtioc1b/tmri1/ poe1# sck9 44 pb4 cts9#/rts9#/ss9# 45 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6
r01ds0041ej0090 rev.0.90 page 24 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. 46 pb2 cts6#/rts6#/ss6# 47 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4-ds 48 vcc 49 pb0 mtic5w rxd6/smiso6/sscl6/rspcka 50 vss 51 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia 52 pa5 rspcka 53 pa4 mtic5u/mtclka/tmri0 txd5/smo si5/ssda5/ssla0 irq5-ds/cvrefb1 54 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5 irq6-ds/cmpb1 55 pa2 rxd5/smiso5/sscl5/ssla3 56 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa 57 pa0 mtioc4a ssla1 cacref 58 pe5 mtioc4c/mtioc2b irq5/an013 59 pe4 mtioc4d/mtioc1a an012/cmpa2 60 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 61 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7-ds/an010/ cvrefb0 62 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 63 pe0 sck12 an008 64 pd2 mtioc4d irq2 65 pd1 mtioc4b irq1 66 pd0 irq0 67 p47 an007 68 p46 an006 69 p45 an005 70 p44 an004 71 p43 an003 72 p42 an002 73 p41 an001 74 vrefl0 75 p40 an000 76 vrefh0 77 avcc0 78 p07 adtrg0# 79 avss0 80 p05 da1 table 1.7 list of pins and pin functions (80-pin lqfp) (2 / 2) pin no. power supply, clock, system control i/o port timers (mtu2, tmr, poe2) communications (scic, scid, rspi, riic) others
r01ds0041ej0090 rev.0.90 page 25 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. table 1.8 list of pins and pin functions (64-pin lqfp) (1 / 2) pin no. power supply, clock, system control i/o port timers (mtu2, tmr, poe2) communication (scic, scid, rspi, riic) others 1p 0 3 da0 2v c l 3m d fined 4x c i n 5 xcout 6r e s # 7x t a l p 3 7 8v s s 9 extal p36 10 vcc 11 p35 nmi 12 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 irq2-ds/rtcout/ rtcic2 13 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 14 p30 mtioc4b/tmri3/poe8# rxd1 /smiso1/sscl1 irq0-ds/rtcic0 15 p27 mtioc2b/tmci3 sck1 finec 16 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 17 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda-ds irq7 18 p16 mtioc3c/mtioc3d/tmo2 txd1/smosi1/ssda1/mosia/ scl-ds irq6/rtcout/ adtrg0# 19 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 irq5 20 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 21 ph3 tmci0 22 ph2 tmri0 irq1 23 ph1 tmo0 irq0 24 ph0 cacref 25 p55 mtioc4d/tmo3 26 p54 mtioc4b/tmci1 27 pc7 mtioc3a/tmo2/mtclkb txd8 /smosi8/ssda8/misoa cacref 28 pc6 mtioc3c/mtclka/tmci2 rxd8/smiso8/sscl8/mosia 29 pc5 mtioc3b/mtclkd/tmri2 sck8/rspcka 30 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 31 pc3 mtioc4d txd5/smosi5/ssda5 32 pc2 mtioc4b rxd5/smiso5/sscl5/ssla3 33 pb7 mtioc3b txd9/smosi9/ssda9 34 pb6 mtioc3d rxd9/smiso9/sscl9 35 pb5 mtioc2a/mtioc1b/tmri1/ poe1# sck9 36 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 37 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4-ds 38 vcc 39 pb0 mtic5w rxd6/smiso6/sscl6/rspcka 40 vss 41 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia 42 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/ssla0 irq5-ds/cvrefb1 43 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5 irq6-ds/cmpb1 44 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa
r01ds0041ej0090 rev.0.90 page 26 of 144 aug 10, 2011 rx210 group 1. overview under development preliminary document specifications in this document are tentative and subject to change. note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. 45 pa0 mtioc4a ssla1 cacref 46 pe5 mtioc4c/mtioc2b irq5/an013 47 pe4 mtioc4d/mtioc1a an012/cmpa2 48 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 49 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7-ds/an010/ cvrefb0 50 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 51 pe0 sck12 an008 52 vrefl 53 p46 an006 54 vrefh 55 p44 an004 56 p43 an003 57 p42 an002 58 p41 an001 59 vrefl0 60 p40 an000 61 vrefh0 62 avcc0 63 p05 da1 64 avss0 table 1.8 list of pins and pin functions (64-pin lqfp) (2 / 2) pin no. power supply, clock, system control i/o port timers (mtu2, tmr, poe2) communication (scic, scid, rspi, riic) others
r01ds0041ej0090 rev.0.90 page 27 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2. cpu the rx210 group is an mcu with the high-sp eed, high-performance rx cpu as its core. a variable-length instruction format has been adopted for the rx cpu. allocating the more frequently used instructions to the shorter instruction lengths facilitates the deve lopment of efficient programs that take up less memory. the cpu has 73 basic instructions and and nine dsp instructions, for a total of 82 instructions. it has 10 addressing modes and caters to register?register operations, regi ster?memory operations, imme diate?register operations, immediate?memory operations, memory?memory transfer, a nd bitwise operations. high-speed operation was realized by achieving execution in a single cycle not only for register?register operations, but also for other types of multiple instructions. the cpu includes an intern al multiplier and an internal divider for high-speed multiplication and division. the rx cpu has a five-stage pipeline for processing instru ctions. the stages are instru ction fetching, instruction decoding, execution, memo ry access, and write-back. in cases where pipeline processing is drawn-out by memory access, subsequent operations may in fact be executed earlier. by adopting ?out-o f-order completion? of this kind, the execution of instructions is controlled to optimize numbers of clock cycles. 2.1 features ? high instruction execution rate: one instruction in one clock cycle ? address space: 4-gbyte linear ? register set of the cpu general purpose: sixteen 32-bit registers control: eight 32-bit registers accumulator: one 64-bit register ? basic instructions: 73 (arithmetic/logic instructions, data-tra nsfer instructions, branch instructions, bit-manipulation instructions, string-manipulation instructions, and system-manipulation instructions) relative branch instructions to suit branch distances variable-length instruction format (lengths from one to eight bytes) short formats for frequently used instructions ? dsp instructions: 9 supports 16-bit ? 16-bit multiplication and mult iply-and-accumulate operations. rounds the data in the accumulator. ? addressing modes: 10 ? five-stage pipeline adoption of out-of-order completion ? processor modes a supervisor mode and a user mode are supported. ? data arrangement selectable as little endian or big endian
r01ds0041ej0090 rev.0.90 page 28 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.2 register set of the cpu the rx cpu has sixteen general-purpos e registers, eight control register s, and one accumulator used for dsp instructions. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt st ack pointer (isp) or user st ack pointer (usp), according to the value of the u bit in the psw register. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) * 1 general-purpose register control register b31 b0 b31 b0 dsp instruction register b63 b0 acc (accumulator)
r01ds0041ej0090 rev.0.90 page 29 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen general-purpose registers (r0 to r15). r1 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by th e value of the stack pointer se lect bit (u) in the processor status word (psw). 2.2.2 control registers this cpu has the following eight control registers. ? interrupt stack pointer (isp) ? user stack pointer (usp) ? interrupt table register (intb) ? program counter (pc) ? processor status word (psw) ? backup pc (bpc) ? backup psw (bpsw) ? fast interrupt vector register (fintv)
r01ds0041ej0090 rev.0.90 page 30 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.2.2.1 interrupt stack pointer (isp)/user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of four, as this reduces th e numbers of cycles required to execute interrupt sequences and instructions entai ling stack manipulation. 2.2.2.2 interrupt ta ble register (intb) the interrupt table register (intb) specifies the address where the relocatable vector table starts. 2.2.2.3 program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. b31 b0 isp value after reset: 00000000000000000000000000000000 b31 b0 usp value after reset: 00000000000000000000000000000000 b31 b0 value after reset: undefined b31 b0 value after reset: contents of addresses fffffffch to ffffffffh
r01ds0041ej0090 rev.0.90 page 31 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.2.2.4 processor status word (psw) note 1. in user mode, writing to the ipl[3:0], pm, u, and i bits by an mvtc or a popc instruction is ignored. writing to the ipl [3:0] bits by an mvtipl instruction generates a privileged instruction exception. note 2. in supervisor mode, writing to the pm bit by an mvtc or a popc instruction is ignored, but writing to the other bits is possible. note 3. switching from supervisor mode to user mode requires execution of an rte instruction after having set the psw.pm bit saved on the stack to 1 or executing an rtfi instruction after having set the bpsw.pm bit to 1. b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 ???? ipl[3:0] ???pm?? u i value after reset: 0000000000000000 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ???????????? o s z c value after reset: 0000000000000000 bit symbol bit name description r/w b0 c carry flag 0: no carry has occurred. 1: a carry has occurred. r/w b1 z zero flag 0: result is non-zero. 1: result is 0. r/w b2 s sign flag 0: result is a positive value or 0. 1: result is a negative value. r/w b3 o overflow flag 0: no overflow has occurred. 1: an overflow has occurred. r/w b15 to b4 ? reserved these bits are read as 0. the write value should be 0. r/w b16 i* 1 interrupt enable 0: interrupt disabled. 1: interrupt enabled. r/w b17 u* 1 stack pointer select 0: interrupt stack pointer (isp) is selected. 1: user stack pointer (usp) is selected. r/w b19, b18 ? reserved these bits are read as 0. the write value should be 0. r/w b20 pm* 1, * 2, * 3 processor mode select 0: supervisor mode is selected. 1: user mode is selected. r/w b23 to b21 ? reserved these bits are read as 0. the write value should be 0. r/w b27 to b24 ipl[3:0]* 1 processor interrupt priority level b27 b24 0 0 0 0: priority level 0 (lowest) 0 0 0 1: priority level 1 0 0 1 0: priority level 2 0 0 1 1: priority level 3 0 1 0 0: priority level 4 0 1 0 1: priority level 5 0 1 1 0: priority level 6 0 1 1 1: priority level 7 1 0 0 0: priority level 8 1 0 0 1: priority level 9 1 0 1 0: priority level 10 1 0 1 1: priority level 11 1 1 0 0: priority level 12 1 1 0 1: priority level 13 1 1 1 0: priority level 14 1 1 1 1: priority level 15 (highest) r/w b31 to b28 ? reserved these bits are read as 0. the write value should be 0. r/w
r01ds0041ej0090 rev.0.90 page 32 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. c flag (carry flag) this flag indicates whether a carry , borrow, or shift-out has occurred as the result of an operation. z flag (zero flag) this flag indicates that the result of an operation was 0. s flag (sign flag) this flag indicates that the result of an operation was negative. o flag (overflow flag) this flag indicates th at an overflow occurred during an operation. i bit (interrupt enable) this bit enables interrupt requests. when an exception is accepte d, the value of this bit becomes 0. u bit (stack pointer select) this bit specifies the stack pointer as ei ther the isp or usp. when an exception re quest is accepted, this bit is set to 0. when the processor mode is switched from supervisor mode to user mode, this bit is set to 1. pm bit (processor mode select) this bit specifies the processor mo de. when an exce ption is accepted, the valu e of this bit becomes 0. ipl[3:0] bits (processor interrupt priority level) the ipl[3:0] bits specify the processor interrupt priority le vel as one of sixteen levels from zero to fi fteen, wherein priority level zero is the lowest and priority level fifteen the highest. when the priority leve l of a requested interrupt is higher than the processor interrupt priority level, the interrup t is enabled. setting the ipl[3:0] bits to level fifteen (fh) disables all interrupt requests. the ipl[3:0] bits are set to le vel fifteen (fh) when a non-maskable interrupt is generated. when interrupts in general are generated, the bits ar e set to the priority levels of accepted interrupts. 2.2.2.5 backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. b31 b0 value after reset: undefined
r01ds0041ej0090 rev.0.90 page 33 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.2.2.6 backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. 2.2.2.7 fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. 2.2.3 register associat ed with dsp instructions 2.2.3.1 accumulator (acc) the accumulator (acc) is a 64-bit register used for dsp instru ctions. the accumulator is also used for the multiply and multiply-and-accumulate inst ructions; emul, emulu, mul, and rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for wr iting to the accumulator. the mvtachi and mvtaclo instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from th e accumulator. the mvfachi and mvfacmi instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively. b31 b0 value after reset: undefined b31 b0 value after reset: undefined range for reading by mvfacmi b63 b48 b47 b32 b31 b16 b15 b0 range for reading and writing by mvtachi and mvfachi range for writing by mvtaclo value after reset: undefined
r01ds0041ej0090 rev.0.90 page 34 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.3 processor mode the rx cpu supports two processor modes, supervisor and user. these processor modes enable the realization of a hierarchical cpu resource protection. each processor mode imposes a level on rights of access to th e cpu resources and the instruct ions that can be executed. supervisor mode carries greater ri ghts than those of user mode. the initial state after a reset is supervisor mode. 2.3.1 supervisor mode in supervisor mode, all cpu resources are accessible and all in structions are available. howe ver, writing to the processor mode select bit (pm) in the processor st atus word (psw) by executing an mvtc or a popc instruction will be ignored. for details on how to write to the pm bit, refer to section 2.2.2.4, processor status word (psw) . 2.3.2 user mode in user mode, write access to the cpu res ources listed below is restricted. the restriction applies to any instruction capable of write access. ? some bits (bits ipl[3:0], pm, u, and i) in the pro cessor status word (psw) ? interrupt stack pointer (isp) ? interrupt table register (intb) ? backup psw (bpsw) ? backup pc (bpc) ? fast interrupt vector register (fintv) 2.3.3 privileged instruction privileged instructions can only be executed in supervisor mode. executing a privileged instruction in user mode produces a privileged instru ction exception. privileged instructions include the rtfi, mvtipl, rte, and wait instructions. 2.3.4 switching between processor modes manipulating the processor mode select bit (pm) in the pr ocessor status word (psw) sw itches the processor mode. however, rewriting to the pm bit by executing an mvtc or a popc instruction is prohibited. switch the processor mode by following the procedures described below. (1) switching from user mode to supervisor mode after an exception has been generated, the psw.pm bit is set to 0 and the cpu switches to supervisor mode. the hardware pre-processing is executed in supervisor mode. the state of the pr ocessor mode before the exception was generated is retained in the copy of psw.pm bit is saved on the stack. (2) switching from supervisor mode to user mode executing an rte instruction when the value of the copy of the psw.pm bit that has been preserved on the stack is 1 or an rtfi instruction when the value of the copy of the psw.pm bit that has b een preserved in the backup psw (bpsw) is 1 causes a transition to user mode. in the transition to user mode, the value of the stack pointer designation bit (the u bit in the psw) becomes 1.
r01ds0041ej0090 rev.0.90 page 35 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.4 data types the rx cpu can handle three types of data: integer, bit, and string. 2.4.1 integer an integer can be signed or unsigned. for signed integers , negative values are represented by two's complements. figure 2.2 integer unsigned longword (32-bit) integer signed longword (32-bit) integer unsigned word (16-bit) integer signed word (16-bit) integer unsigned byte (8-bit) integer signed byte (8-bit) integer s: signed bit b31 b0 b31 b0 b15 b0 b15 b0 b7 b0 b7 b0 s s s
r01ds0041ej0090 rev.0.90 page 36 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.4.2 bit wise operations five bit-manipulation instructions are provided for b itwise operations: bclr, bmcnd, bnot, bset, and btst. a bit in a register is specified as the destination register and a bit number in the range from 31 to 0. a bit in memory is specified as the dest ination address and a bit number from 7 to 0. the addressing modes available to specify addresses are register i ndirect and register relative. figure 2.3 bit 2.4.3 strings the string data type consists of an arbitrary number of consecutive byte (8-bit), wo rd (16-bit), or longword (32-bit) units. seven string manipulation instructions are provided for use with strings: scmpu, smovb, smovf, smovu, sstr, suntil, and swhile. figure 2.4 string register b31 b0 #bit, rn (bit: 31 to 0, n: 0 to 15) b7 b0 #bit, mem (bit: 7 to 0) memory example example #30,r1 (register r1, bit 30) #2,[r2] (address [r2], bit 2) string of byte (8-bit) data 8 string of word (16-bit) data 16 string of longword (32-bit) data 32
r01ds0041ej0090 rev.0.90 page 37 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.5 endian for the rx cpu, instructions are little endian, but the treatment of data is selectable as litt le or big endian. 2.5.1 switching the endian as arrangements of bytes, the rx210 group supports both big endian, where the higher-order byte (msb) is at location 0, and little endian, where the lower-order byte (lsb) is at location 0. for details on the endian setting, see section 3, operating modes . operations for access differ according to the endian setting and, depending on the instruction, whethe r 8-, 16- or 32-bit access has been selected. operations for access in the various possible cases are described in table 2.1 to table 2.12 . in the tables, ll indicates bits d7 to d0 of the general-purpose register, lh indicates bits d15 to d8 of the general-purpose register, hl indicates bits d23 to d16 of the general-purpose register, and hh indicates bits d31 to d24 of the general-purpose register. d31 to d24 d23 to d16 d15 to d8 d7 to d0 general purpose register: rm hh hl lh ll table 2.1 32-bit read operations when little endian has been selected operation address of src reading a 32-bit unit from address 0 reading a 32-bit unit from address 1 reading a 32-bit unit from address 2 reading a 32-bit unit from address 3 reading a 32-bit unit from address 4 address 0 transfer to ll ? ? ? ? address 1 transfer to lh transfer to ll ? ? ? address 2 transfer to hl transfer to lh transfer to ll ? ? address 3 transfer to hh transfer to hl transfer to lh transfer to ll ? address 4 ? transfer to hh transfer to hl transfer to lh transfer to ll address 5 ? ? transfer to hh transfer to hl transfer to lh address 6 ? ? ? transfer to hh transfer to hl address 7 ? ? ? ? transfer to hh table 2.2 32-bit read operations when big endian has been selected operation address of src reading a 32-bit unit from address 0 reading a 32-bit unit from address 1 reading a 32-bit unit from address 2 reading a 32-bit unit from address 3 reading a 32-bit unit from address 4 address 0 transfer to hh ? ? ? ? address 1 transfer to hl transfer to hh ? ? ? address 2 transfer to lh transfer to hl transfer to hh ? ? address 3 transfer to ll transfer to lh transfer to hl transfer to hh ? address 4 ? transfer to ll transfer to lh transfer to hl transfer to hh address 5 ? ? transfer to ll transfer to lh transfer to hl address 6 ? ? ? transfer to ll transfer to lh address 7 ? ? ? ? transfer to ll
r01ds0041ej0090 rev.0.90 page 38 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. table 2.3 32-bit write operations when little endian has been selected operation address of dest writing a 32-bit unit to address 0 writing a 32-bit unit to address 1 writing a 32-bit unit to address 2 writing a 32-bit unit to address 3 writing a 32-bit unit to address 4 address 0 transfer from ll ? ? ? ? address 1 transfer from lh transfer from ll ? ? ? address 2 transfer from hl transfer from lh transfer from ll ? ? address 3 transfer from hh transfer from hl transfer from lh transfer from ll ? address 4 ? transfer from hh transfer from hl transfer from lh transfer from ll address 5 ? ? transfer from hh transfer from hl transfer from lh address 6 ? ? ? transfer from hh transfer from hl address 7 ? ? ? ? transfer from hh table 2.4 32-bit write operations when big endian has been selected operation address of dest writing a 32-bit unit to address 0 writing a 32-bit unit to address 1 writing a 32-bit unit to address 2 writing a 32-bit unit to address 3 writing a 32-bit unit to address 4 address 0 transfer from hh ? ? ? ? address 1 transfer from hl transfer from hh ? ? ? address 2 transfer from lh transfer from hl transfer from hh ? ? address 3 transfer from ll transfer from lh transfer from hl transfer from hh ? address 4 ? transfer from ll transfer from lh transfer from hl transfer from hh address 5 ? ? transfer from ll transfer from lh transfer from hl address 6 ? ? ? transfer from ll transfer from lh address 7 ? ? ? ? transfer from ll
r01ds0041ej0090 rev.0.90 page 39 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. table 2.5 16-bit read operations when little endian has been selected operation address of src reading a 16-bit unit from address 0 reading a 16-bit unit from address 1 reading a 16-bit unit from address 2 reading a 16-bit unit from address 3 reading a 16-bit unit from address 4 reading a 16-bit unit from address 5 reading a 16-bit unit from address 6 a d d r e s s 0t r a n s f e r t o l l?????? a d d r e s s 1t r a n s f e r t o l h t r a n s f e r t o l l????? a d d r e s s 2?t r a n s f e r t o l h t r a n s f e r t o l l???? address 3 ? ? transfer to lh transfer to ll ? ? ? address 4 ? ? ? transfer to lh transfer to ll ? ? a d d r e s s 5????t r a n s f e r t o l h t r a n s f e r t o l l? a d d r e s s 6?????t r a n s f e r t o l h t r a n s f e r t o l l a d d r e s s 7??????t r a n s f e r t o l h table 2.6 16-bit read operations when big endian has been selected operation address of src reading a 16-bit unit from address 0 reading a 16-bit unit from address 1 reading a 16-bit unit from address 2 reading a 16-bit unit from address 3 reading a 16-bit unit from address 4 reading a 16-bit unit from address 5 reading a 16-bit unit from address 6 a d d r e s s 0t r a n s f e r t o l h?????? a d d r e s s 1t r a n s f e r t o l l t r a n s f e r t o l h????? a d d r e s s 2?t r a n s f e r t o l l t r a n s f e r t o l h???? address 3 ? ? transfer to ll transfer to lh ? ? ? address 4 ? ? ? transfer to ll transfer to lh ? ? a d d r e s s 5????t r a n s f e r t o l l t r a n s f e r t o l h? a d d r e s s 6?????t r a n s f e r t o l l t r a n s f e r t o l h a d d r e s s 7??????t r a n s f e r t o l l
r01ds0041ej0090 rev.0.90 page 40 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. table 2.7 16-bit write operations when little endian has been selected operation address of dest writing a 16-bit unit to address 0 writing a 16-bit unit to address 1 writing a 16-bit unit to address 2 writing a 16-bit unit to address 3 writing a 16-bit unit to address 4 writing a 16-bit unit to address 5 writing a 16-bit unit to address 6 a d d r e s s 0t r a n s f e r f r o m l l?????? a d d r e s s 1 t r a n s f e r f r o m l h t r a n s f e r f r o m l l????? a d d r e s s 2?t r a n s f e r f r o m l h t r a n s f e r f r o m l l???? address 3 ? ? transfer from lh transfer from ll ? ? ? address 4 ? ? ? transfer from lh transfer from ll ? ? a d d r e s s 5????t r a n s f e r f r o m l h t r a n s f e r f r o m l l? a d d r e s s 6?????t r a n s f e r f r o m l h t r a n s f e r f r o m l l a d d r e s s 7??????t r a n s f e r f r o m l h table 2.8 16-bit write operations when big endian has been selected operation address of dest writing a 16-bit unit to address 0 writing a 16-bit unit to address 1 writing a 16-bit unit to address 2 writing a 16-bit unit to address 3 writing a 16-bit unit to address 4 writing a 16-bit unit to address 5 writing a 16-bit unit to address 6 a d d r e s s 0t r a n s f e r f r o m l l?????? a d d r e s s 1 t r a n s f e r f r o m l h t r a n s f e r f r o m l l????? a d d r e s s 2?t r a n s f e r f r o m l h t r a n s f e r f r o m l l???? address 3 ? ? transfer from lh transfer from ll ? ? ? address 4 ? ? ? transfer from lh transfer from ll ? ? a d d r e s s 5????t r a n s f e r f r o m l h t r a n s f e r f r o m l l? a d d r e s s 6?????t r a n s f e r f r o m l h t r a n s f e r f r o m l l a d d r e s s 7??????t r a n s f e r f r o m l h
r01ds0041ej0090 rev.0.90 page 41 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.5.2 access to i/o registers the addresses of i/o registers are fixed, and this is regard less of whether the setting is for little endian or big endian. accordingly, changes to the endi an do not affect access to i/o registers. for the arrangements of i/o registers, refer to the descriptions of registers in the relevant sections. table 2.9 8-bit read operations when little endian has been selected operation address of src reading an 8-bit unit from address 0 reading an 8-bit unit from address 1 reading an 8-bit unit from address 2 reading an 8-bit unit from address 3 address 0 transfer to ll ? ? ? address 1 ? transfer to ll ? ? address 2 ? ? transfer to ll ? address 3 ? ? ? transfer to ll table 2.10 8-bit read operations when big endian has been selected operation address of src reading an 8-bit unit from address 0 reading an 8-bit unit from address 1 reading an 8-bit unit from address 2 reading an 8-bit unit from address 3 address 0 transfer to ll ? ? ? address 1 ? transfer to ll ? ? address 2 ? ? transfer to ll ? address 3 ? ? ? transfer to ll table 2.11 8-bit write operations when little endian has been selected operation address of dest writing an 8-bit unit to address 0 writing an 8-bit unit to address 1 writing an 8-bit unit to address 2 writing an 8-bit unit to address 3 address 0 transfer from ll ? ? ? address 1 ? transfer from ll ? ? address 2 ? ? transfer from ll ? address 3 ? ? ? transfer from ll table 2.12 8-bit write operations when big endian has been selected operation address of dest writing an 8-bit unit to address 0 writing an 8-bit unit to address 1 writing an 8-bit unit to address 2 writing an 8-bit unit to address 3 address 0 transfer from ll ? ? ? address 1 ? transfer from ll ? ? address 2 ? ? transfer from ll ? address 3 ? ? ? transfer from ll
r01ds0041ej0090 rev.0.90 page 42 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.5.3 notes on access to i/o registers ensure that access to i/o registers is in accord with the following rules. ? with i/o registers for which a bus width of eight bits is indicated, use instructions having operands of the same width (eight bits). that is, access these re gisters by using instructions with .b as the size specifier (.size), or with .b or .ub as the size-extens ion specifier (.memex). ? with i/o registers for which a bus width of 16 bits is indi cated, use instructions having operands of the same width (16 bits). that is, access these registers by using instructions with .w as the size specifier (.size), or with .w or .uw as the size-extension specifier (.memex). ? with i/o registers for which a bus width of 32 bits is indi cated, use instructions having operands of the same width (32 bits). that is, access these registers by using instructions with .l as the size specifier (.size), or with .l size- extension specifier (.memex).
r01ds0041ej0090 rev.0.90 page 43 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.5.4 data arrangement 2.5.4.1 data arrangem ent in registers figure 2.5 shows the relation between the sizes of registers and bit numbers. figure 2.5 data arrangement in registers 2.5.4.2 data arrangement in memory data in memory have three sizes: byte (8-bit), word (16-bi t), and longword (32-bit). the da ta arrangement is selectable as little endian or big endian. figure 2.6 shows the arrangement of data in memory. figure 2.6 data arra ngement in memory 2.5.5 notes on the alloca tion of instruction codes the allocation of instruction codes to an external space where the endian differs from that of the chip is prohibited. if the instruction codes are allocated to the exte rnal space, they must be allocated to ar eas where the endian setting is the same as that for the chip. longword (32-bit) data b31 b0 b15 b0 b7 b0 word (16-bit) data byte (8-bit) data msb lsb 1-bit data (little endian) (big endian) address l address l byte data word data address m address m+1 address n address n+1 address n+2 address n+3 longword data data image data type b7 b0 lsb msb data image address 7 6 5 4 3 2 1 0 lsb lsb msb msb b7 b0 lsb msb 7 6 5 4 3 2 1 0 lsb lsb msb msb
r01ds0041ej0090 rev.0.90 page 44 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.6 vector table there are two types of vector table: fixed and relocatable. each vector in the vector table consis ts of four bytes and specifies the address wher e the corresponding exception handling routine starts. 2.6.1 fixed vector table the fixed vector table is allocated to a fixed address range. the individual vectors for the privileged instruction exception, undefined instruction exception, non-maskable interrup t, and reset are allocated to addresses in the range from ffffff80h to ffffffffh. figure 2.7 shows the fixed vector table. figure 2.7 fixed vector table (reserved) (reserved) (reserved) privileged instruction exception (reserved) undefined instruction exception (reserved) (reserved) (reserved) (reserved) (reserved) lsb (reserved) non-maskable interrupt reset msb ffffffdch fffffffch ffffffe0h ffffffe4h ffffffe8h ffffffech fffffff0h fffffff4h fffffff8h ffffffd0h ffffffd4h ffffffd8h ffffffcch ffffff80h
r01ds0041ej0090 rev.0.90 page 45 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.6.2 relocatable vector table the address where the relocatable vector ta ble is placed can be adjusted. the table is a 1,024-byte region that contains all vectors for unconditional traps and interrupts and starts at th e address (intbase) specified in the interrupt table register (intb). figure 2.8 shows the relocatable vector table. each vector in the relocatable vector table has a vector number from 0 to 255 . each of the int instructions, which act as the sources of unconditional traps, is allocat ed to the vector that has the same numb er as is specified as the operand of the instruction itself (from 0 to 255). the brk instruction is allo cated to the vector with numb er 0. furthermore, vector numbers (from 0 to 255) are allocated to interrupt requests in a fixed way for each product. for more on interrupt vector numbers, see section 14.3.1, interrupt vector table . figure 2.8 relocatable vector table intb 0 intbase+4 intbase b31 b0 intbase+8 255 intbase+1020 interrupt vectors are allocated in this order. 1 2
r01ds0041ej0090 rev.0.90 page 46 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.7 operation of instructions 2.7.1 data prefetching by the rmpa instruction and the string-manipulation instructions the rmpa instruction and the string-manipulation instructio ns except the sstr instruction (that is, scmpu, smovb, smovf, smovu, suntil, and swhile inst ructions) may prefetch data from the memory to speed up the read processing. data is pref etched from the prefetch ing start position with three bytes as the upper limit. the prefetching start positions of each oper ation are shown below. ? rmpa instruction: the multiplica nd address specified by r1, and th e multiplier address specified by r2 ? scmpu instruction: the source address specified by r1 for comp arison, and the destination address specified by r2 for comparison ? suntil and swhile instructio ns: the destination address sp ecified by r1 for comparison ? smovb, smovf, and smovu instructions: the so urce address specified by r2 for transfer
r01ds0041ej0090 rev.0.90 page 47 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.8 pipeline 2.8.1 overview the rx cpu has 5-stage pipeline structur e. the rx cpu instruction is converte d into one or more micro-operations, which are then executed in pipelin e processing. in the pipeline stage, the if stage is executed in the unit of instructions, while the d and subsequent stages are ex ecuted in the unit of micro-operations. the operation of pipeline and respective stages is described below. (1) if stage (instruction fetch stage) in the if stage, the cpu fetc hes instructions from the memory. as the rx cpu has four 4-byte instruction queues, it fetches instructions until the instruction queue is full, regardless of the completion of decoding in the d (decoding) stage. (2) d stage (decoding stage) the cpu decodes instructions in the d stage and converts them into micro-operations. the cpu reads the register information (rf) in this stage and executes a bypass process (byp) if the result of the preceding instruc tion will be used in a subsequent instruction. the write of operation result to the register (rw) can be execute d with the register reference by using the bypass process. (3) e stage (execution stage) operations and address calculations (op) are pr ocessed in the e stage. (4) m stage (memory access stage) operand memory accesses (oa1, oa2) are processed in the m stage. this stage is used only when the memory is accessed, and is divided into two sub-stages, m1 and m2. the rx cpu enables respective memory accesses for m1 and m2. ? m1 stage (memory-access stage 1) operand memory access (oa1) is processed. store operation: the pipeline processing ends when a write re quest is received via the bus. load operation: the oper ation proceeds to the m2 stage when a read request is received via the bus. if a request and load data are received at the same timing (no-wait memory access), the operation proceeds to the wb stage. ? m2 stage (memory-access stage 2) operand memory access (oa2) is processed. the cpu waits for the lo ad data in the m2 stage. when the load data is received, the operation proceeds to the wb stage. (5) wb stage (write-back stage) the operation result and the data read from memory are written to the register (rw) in the wb stage. the data read from memory and the other type of data, such as the operation result, can be written to the register in the same clock cycles.
r01ds0041ej0090 rev.0.90 page 48 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. figure 2.9 shows the pipeline configuration and its operation. figure 2.9 pipeline configuration and its operation if dec op oa1 oa2 if stage byp rf pipeline stage execution processing d stage e stage m1 stage m2 stage one cycle wb stage rw m stage
r01ds0041ej0090 rev.0.90 page 49 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.8.2 instructions an d pipeline processing the operands in the table belo w indicate the following meaning. #imm: immediate rs, rs2, rd, rd2, ri, rb: general-pu rpose register, cr: control register dsp: dsp5, dsp8, dsp16, dsp24 pcdsp: pcdsp3, pcdsp8, pcdsp16, pcdsp24 2.8.2.1 instructions converted into singl e micro-operation and pipeline processing the table below lists the instructions that are converted into a single micro-operation. the number of cycl es in the table indicates the number of cycl es during no-wait memory access. note 1. the number of cycles for the dividing inst ruction varies according to the divisor and dividend. note 2. for the number of cycles for throughput and latency, see section 2.8.3, calculation of the instruction processing time. table 2.13 instructions that are converted into a single micro-operation instruction mnemonic (indicates the common operation when the size is omitted) reference figure number of cycles arithmetic/logic instructions (register-register, immediate-register) except emul, emulu, rmpa, div, divu and satr ? {abs, adc, add, and, cmp, max, min, mul, neg, nop, not, or, rolc, rorc, rotl, rotr, sat, sbb, shar, shll, shlr, sub, tst, xor} ?#imm, rd?/?rd?/ ?rs, rd?/?rs, rs2, rd? figure 2.10 1 arithmetic/logic instructions (division) ? div ?#imm, rd?/?rs, rd? figure 2.10 3 to 20* 1 ? divu ?#imm, rd?/?rs, rd? figure 2.10 2 to 18* 1 data transfer instructions (register-register, immediate-register) ? {mov, movu, revl, revw} ?#imm, rd?/?rs, rd? ? sc cnd ?rd? ? {stnz, stz} ?#imm, rd? figure 2.10 1 transfer instructions (load operation) ? {mov, movu} ?[rs], rd?/?dsp[rs], rd?/?[rs+], rd?/ ?[?rs], rd?/?rs, [ri, rb]? ? pop ?rd? figure 2.11 throughput: 1 latency: 2* 2 transfer instructions (store operation) ? mov ?rs, [rd]?/?rs, dsp[rd]?/?rs, [rd+]?/?rs, [?rd]?/ ?rs, [ri, rb]? ? push ?rs? ? pushc ?cr? figure 2.12 1 bit manipulation instructions (register) ? {bclr, bnot, bset, btst} ?#imm, rd?/?rs, rd? ? bm cnd ?#imm, rd? figure 2.10 1 branch instructions ? b cnd ?pcdsp? ? {bra, bsr} ?pcdsp?/?rs? ? {jmp, jsr} ?rs? figure 2.20 branch taken: 3 branch not taken: 1 system manipulation instructions ? clrpsw, setpsw ?#imm? ? mvtc ?#imm, cr?/?rs, cr? ? mvfc ?cr, rd? ? mvtipl?#imm? ?1 dsp instructions ? {machi, maclo, mulhi, mullo} ?rs, rs2? ? {mvfachi, mvfacmi} ?rd? ? {mvtachi, mvtaclo} ?rs? ? racw?#imm? figure 2.10 1
r01ds0041ej0090 rev.0.90 page 50 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. figure 2.10 to figure 2.12 show the operation of instructions that are converted into a basic single micro-operation. figure 2.10 operation for regist er-register, immediate-register figure 2.11 load operation figure 2.12 store operation if d e wb add r1, r2 4 stages if d e wb div r3, r4 e note: ? multi-cycle instructions (div, divu) ar e executed in multiple cycles in the e stage. if d e wb mov [r1], r2 m1 if d e wb mov [r1], r2 m1 m1 note: ? when the load operation is executed to the no-wait memory, the m1 stage is executed in one cycle. in other cases, the m stage (m1 or m2) is executed in multiple cycles. 5 stages m2 if d e 4 stages m1 if d e m1 m1 note: ? the m1 stage is executed until a write request is received during the store operation. (if the store operation is executed to the no -wait memory, the m1 stage is executed in one cycle.) m1 mov r2, [r1]
r01ds0041ej0090 rev.0.90 page 51 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.8.2.2 instructions converted into multiple micro-operations a nd pipeline processing the table below lists the instructions th at are converted into multi ple micro-operations. the number of cycles in the table indicates the number of cycl es during no-wait memory access. table 2.14 instructions that are converted into multiple micro-operations (1/2) instruction mnemonic (indicates the common operation when the size is omitted) reference figure number of cycles arithmetic/logic instructions (memory source operand) ? {adc, add, and, cmp, max, min, mul, or, sbb, sub, tst, xor} ?[rs], rd?/?dsp[rs], rd? figure 2.13 3 arithmetic/logic instructions (division) ? div ?[rs],rd / dsp[rs],rd? ? 5 to 22 ? divu?[rs],rd / dsp[rs],rd? ? 4 to 20 arithmetic/logic instructions (multiplier: 32 32 ? 64 bits) (register-register, register- immediate) ? {emul, emulu} ?#imm, rd?/?rs, rd? figure 2.15 2 arithmetic/logic instructions (multiplier: 32 32 ? 64 bits) (memory source operand) ? {emul, emulu} ?[rs], rd?/?dsp[rs], rd? ? 4 arithmetic/logic instructions (multiply-and-accumulate operation) ? rmpa.b ? 6+7floor(n/4)+4(n%4) n: number of processing bytes* 1 ? rmpa.w ? 6+5floor(n/2)+4(n%2) n: number of processing words* 1 ? rmpa.l ? 6+4n n: number of processing longwords* 1 arithmetic/logic instructions (64- bit signed saturation processing for the rmpa instruction) ? satr ? 3 data transfer instructions (memory-memory transfer) ? mov ?[rs], [rd]?/?dsp[rs], [rd]?/?[rs], dsp[rd]?/ ?dsp[rs], [rd]? ? push ?[rs]?/?dsp[rs]? figure 2.14 3 bit manipulation instructions (memory source operand) ? {bclr, bnot, bset, btst} ?#imm, [rd]?/ ?#imm, dsp[rd]? ? bm cnd ?#imm, [rd]?/?#imm, dsp[rd]? figure 2.14 3 transfer instructions (load operation) ? popc ?cr? ? throughput: 3 latency: 4* 2 transfer instructions (save operation of multiple registers) ? pushm ?rs-rs2? ? n n: number of registers* 3 transfer instructions (restore operation of multiple registers) ? popm ?rs-rs2? ? throughput: n latency: n + 1 n: number of registers* 2, * 4 transfer instructions (register-register) ? xchg ?rs, rd? figure 2.16 2 transfer instructions (memory-register) ? xchg ?[rs], rd?/?dsp[rs], rd? figure 2.17 2 branch instructions ? rts ? 5 ? rtsd ?#imm? ? 5 ? rtsd ?#imm, rd-rd2? ? throughput: n<5?5:1+n latency: n<4?5:2+n n: number of registers* 2
r01ds0041ej0090 rev.0.90 page 52 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. ?: conditional operator note 1. floor(x): max. integer that is smaller than x note 2. for the number of cycles for throughput and latency, see section 2.8.3, calculation of the instruction processing time. note 3. the pushm instruction is converted into multiple store operations. the pipelin e processing is the same as the one for th e store operations of the mov instruction, where the operation is repeated for the number of specified registers. note 4. the popm instruction is converted into multiple load oper ations. the pipeline processing is the same as the one for the load operations of the mov instruction, where the operation is repeated for the number of specified registers. note 5. each of the scmpu, smovu, swhile, and suntil instructions ends the execution regardless of the specified cycles, if the end condition is satisf ied during execution. string manipulation instructions* 5 ? scmpu ? 2+4floor(n/4)+4(n%4) n: number of comparison bytes* 1 ? smovb ? n>3? 6+3floor(n/4)+3(n%4): 2+3n n: number of transfer bytes* 1 ? smovf, smovu ? 2+3floor(n/4)+3(n%4) n: number of transfer bytes* 1 ? sstr.b ? 2+floor(n/4)+n%4 n: number of transfer bytes* 1 ? sstr.w ? 2+floor(n/2)+n%2 n: number of transfer words* 1 ? sstr.l ? 2+n n: number of transfer longwords ? suntil.b, swhile.b ? 3+3floor(n/4)+3(n%4) n: number of comparison bytes* 1 ? suntil.w, swhile.w ? 3+3floor(n/2)+3(n%2) n: number of comparison words* 1 ? suntil.l, swhile.l ? 3+3n n: number of comparison longwords system manipulation instructions ? rte ? 6 ? rtfi ? 3 table 2.14 instructions that are converted into multiple micro-operations (2/2) instruction mnemonic (indicates the common operation when the size is omitted) reference figure number of cycles
r01ds0041ej0090 rev.0.90 page 53 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. figure 2.13 to figure 2.19 show the operation of instructions that are converted into basic multiple micro-operations. note: ? mop: micro-operation, stall: pipeline stall figure 2.13 arithmetic/logic instruction (memory source operand) figure 2.14 mov instruction (memo ry-memory), bit manipu lation instruction (memory source operand) figure 2.15 emul, emulu instructions (r egister- register, register-immediate) figure 2.16 xchg instruction (registers) figure 2.17 xchg instruction (memory source operand) if d e add [r1], r2 m1 stall e wb d (mop1) load (mop2) add bypass process if d e mov [r1], [r2] m1 load data bit manipulation, store operation (mop1) load (mop2) bit manipulation, store d e m1 m1 if d e emul r2, r4 wb d (mop1) emul-1 (mop2) emul-2 wb write to r4 write to r5 e if d e xchg r1, r2 d (mop1) xchg-1 read from/write to the register (mop2) xchg-2 write to the register wb e wb if d e xchg [r1], r2 d (mop1) load (mop2) store wb e m1 m1
r01ds0041ej0090 rev.0.90 page 54 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.8.2.3 pipeline basic operation in the ideal pipeline processing, each stag e is executed in one cycle, though all instructions may not be pipelined in due to the processing in each st age and the branch execution. the cpu controls the pipeline stage with the if stage in the unit of instructions, while the d and subsequent stages in the unit of micro-operations. the figures below show the pipeline processing of typical cases. note: ? mop: micro-operation, stall: pipeline stall (1) pipeline flow with stalls figure 2.18 when an instruction which requires multiple cycles is executed in the e stage figure 2.19 when an instruction which requires more than one cycle for its operand access is executed figure 2.20 when a branch instruction is executed (an unconditional branch instruction is executed or the condition is satisfied for a conditional branch instruction) figure 2.21 when the subsequent instruction uses an operand read from the memory if div r1, r2 add r3, r4 d e e e wb if d stall e wb stall if stall e wb d stall add r5, r6 (mop) div (mop) add (mop) add if mov [r1], r2 mov [r3], r4 d e m m wb if d e m wb stall if d wb e stall add r5, r6 m stall stall other than no-wait memory access (mop) load (mop) load (mop) add if d e branch instruction branch instruction is executed if d e wb branch penalty two cycles (mop) jump if d e mov [r2], r1 m wb if d stall e wb add r2, r1 bypass process (mop) load (mop) add
r01ds0041ej0090 rev.0.90 page 55 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. (2) pipeline flow with no stall (a) bypass process even when the result of the preceding in struction will be used in a subsequent instruction, the operation processing between registers is pipelined in by the bypass process. figure 2.22 bypass process (b) when wb stages for the memory load and for the operation are overlapped even when the wb stages for the memory load and for the operation are overlapped, the operation processing is pipelined in, because the load data and the operation result can be written to the register at the same timing. figure 2.23 when wb stages for the memory load and for the operation are overlapped (c) when subsequent instruction writes to the same register before the end of memory load even when the subsequent instruction writes to the same register before the end of memory load, the operation processing is pipelined in, because the wb stage for the memory load is canceled. figure 2.24 when subsequent instruction writes to the same register before the end of memory load if d e add r1, r2 sub r3, r2 wb if d e wb bypass process (mop) add (mop) sub if d e mov [r1], r2 if d e wb add r5, r3 m wb (mop) add (mop) load executed at the same timing even when the wb stages are overlapped if d e mov [r1], r2 if d e wb m wb m if d e wb if d e wb ? (mop) load (canceled when the register number matches either of them)
r01ds0041ej0090 rev.0.90 page 56 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. (d) when the load data is not used by the subsequent instruction when the load data is not used by the subsequent instructio n, the subsequent operations are in fact executed earlier and the operation processing ends (out-of-order completion). figure 2.25 when load data is not used by the subsequent instruction 2.8.3 calculation of the in struction processing time though the instruction processing time of the cpu varies acco rding to the pipeline processing, the approximate time can be calculated in the following methods. ? count the number of cycles (see table 2.13 and table 2.14 ) ? when the load data is used by the subsequent instruction, the number of cycles described as ?latency? is counted as the number of cycles for the memory lo ad instruction. for the cycles other th an the memory load instruction, the number of cycles described as ?throughput? is counted. ? if the instruction fetch stall is genera ted, the number of cycles increments. ? depending on the system configur ation, multiple cycles are required for the memory access. if d e mov [r1], r2 if d e m m m wb wb if d e wb add r4, r5 sub r6, r7 (mop) load (mop) add (mop) sub
r01ds0041ej0090 rev.0.90 page 57 of 144 aug 10, 2011 rx210 group 2. cpu under development preliminary document specifications in this document are tentative and subject to change. 2.8.4 numbers of cycles fo r response to interrupts table 2.15 lists numbers of cycles taken by processing for response to interrupts. times calculated from the values in table 2.15 will be applicable when access to memory from the cpu is processed with no waiting. the on -chip ram and rom in products of the rx210 groups allow such access. numbers of cycles for response to interrupts can be minimized by placing progra m code (and vectors) in on-chip rom and the stack in on- chip ram. furthermore, place the addresses where the ex ception handling routine start on eight-byte boundaries. for information on the number of cycles from notif ication to acceptance of the interrup t request, indicated by n in the table above, see table 2.13, instructions that are converted into a single micro-operation , and table 2.14, instructions that are converted into multiple micro-operations . the timing of interrupt acceptance depends on the state of the pipelines. for more information on this, see section 13.3.1, acceptance timing and saved pc value . table 2.15 numbers of cycles for response to interrupts type of interrupt request/details of processing fast interrupt other interrupts icua judgment of priority order 2 cycles cpu number of cycles from noti fication to acceptance of the interrupt request n cycles (varies with the instruction being exec uted at the time the interrupt was received) cpu pre-processing by hardware saving the current pc and psw values in ram (or in control registers in the case of the fast interrupt) reading of the vector branching to the start of the exception handling routine 4 cycles 6 cycles
r01ds0041ej0090 rev.0.90 page 58 of 144 aug 10, 2011 rx210 group 3. address space under development preliminary document specifications in this document are tentative and subject to change. 3. address space 3.1 address space this lsi has a 4-gbyte address space, consisting of the rang e of addresses from 0000 0000 h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps in the re spective operating modes. accessible areas will differ according to the operating mode and states of control bits.
r01ds0041ej0090 rev.0.90 page 59 of 144 aug 10, 2011 rx210 group 3. address space under development preliminary document specifications in this document are tentative and subject to change. figure 3.1 memory map in each operating mode reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 on-chip rom (e2 data flash) (8kb) reserved area* 3 0000 0000h 0008 0000h ffff ffffh single-chip mode* 1 on-chip ram* 2 on-chip rom (program rom) (read only)* 2 0010 0000h peripheral i/o registers 0010 2000h 0080 0000h 0100 0000h on-chip rom (program rom) (write only) (512kb) fff8 0000h ff7f c000h on-chip rom (user boot) (read only) (16kb) fcu-ram (8kb)* 4 peripheral i/o registers peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0001 0000h ff80 0000h 00f8 0000h on-chip rom (fcu firmware)* 4 (read only) (8kb) feff e000h ff00 0000h reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 0000 0000h 0008 0000h ffff ffffh on-chip rom enabled extended mode on-chip ram* 2 on-chip rom (program rom) (read only)* 2 0010 0000h peripheral i/o registers 0010 2000h on-chip rom (e2 data flash) (8kb) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) (512kb) 0800 0000h fff8 0000h ff7f c000h on-chip rom (user boot) (read only) (16kb) fcu-ram (8kb)* 4 peripheral i/o registers peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0001 0000h external address space ff80 0000h 00f8 0000h on-chip rom (fcu firmware)* 4 (read only) (8kb) feff e000h ff00 0000h 0500 0000h reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode on-chip ram* 2 0010 0000h peripheral i/o registers 0100 0000h 0800 0000h ff00 0000h 0001 0000h external address space external address space 0500 0000h note 1. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. note 2. the capacity of rom/ram differs depending on the products. note:?see table 1.3, list of products, for the product type name. note 3. reserved areas should not be accessed. note 4. for details on the fcu, see section 39, rom (flash memory for code storage) and section 40, e2 dataflash memory (flash memory for data storage). rom (byt) ram (byt) capacity address capacity address 512 kbytes fff8 0000h to ffff ffffh 64 kbytes 0000 0000h to 0000 ffffh 384 kbytes fffa 0000h to ffff ffffh 256 kbytes fffc 0000h to ffff ffffh 32 kbytes 0000 0000h to 0000 7fffh 128 kbytes fffe 0000h to ffff ffffh 20 kbytes 0000 0000h to 0000 4fffh
r01ds0041ej0090 rev.0.90 page 60 of 144 aug 10, 2011 rx210 group 3. address space under development preliminary document specifications in this document are tentative and subject to change. 3.2 external address space the external address space is divided into up to four cs areas (c s0 to cs3), each correspo nding to the csn# signal output from a csn# (n = 0 to 3) pin. figure 3.2 shows the address ranges corresponding to the indivi dual cs areas (cs0 to cs3) in on-chip rom disabled extended mode. figure 3.2 correspondence between external address spaces and cs areas (in on-chip rom disabl ed extended mode) 0500 0000h 0600 0000h 0700 0000h cs3 (16mb) 05ff ffffh 06ff ffffh 07ff ffffh cs2 (16mb) cs1 (16mb) ffff ffffh ff00 0000h cs0 (16mb) note 1. reserved areas should not be accessed. note 2. the cs0 area is disabled in on-chip rom enabled extended mode. in this mode, the address space for addresses above 0800 0000h is as shown in figure on this section ?memory map in each operating mode?. reserved area* 1 reserved area* 1 reserved area* 1 reserved area* 1 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode on-chip ram 0010 0000h peripheral i/o registers 0100 0000h 0800 0000h ff00 0000h 0001 0000h external address space* 2 external address space 0500 0000h
r01ds0041ej0090 rev.0.90 page 61 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 4. i/o registers this section gives information on the on- chip i/o register addresses and bit conf iguration. the information is given as shown below. notes on writing to registers are also given at the end. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? numbers of cycles for access indicate numbers of cycles of the given base clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o register , the cpu starts executing the subsequent instru ction before completing i/o register write. this may cause the subsequent instruction to be executed befo re the post-update i/o register value is reflected on the operation. as described in the following examples, sp ecial care is required for the cases in wh ich the subsequent instruction must be executed after the post-update i/o re gister value is actually reflected. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request enab le bit) cleared to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0041ej0090 rev.0.90 page 62 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instruc tion should be executed after th e write operati ons are entirely completed, only read the i/o register that was last written to and execute the operation using th e value; it is not necessary to read or execute operation for all the registers that were written to. (3) number of access cycles to i/o registers for numbers of clock cycles fo r access to i/o registers, see table 4.1, list of i/o registers (address order) . the number of access cycles to i/o regist ers is obtained by following equation. * 1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for internal peripheral bus 1 to 6 the number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed. when peripheral functions connected to internal peripheral bus 2 to 6 or registers for the ex ternal bus control unit (except for bus error related registers) are accessed, the number of divided clock synchronization cycles is added. the number of divided clock synchronization cycles differs depending on the frequency ratio between iclk and pclk (or fclk, bclk) or bus access timing. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access cycles shown in table 4.1 . when the frequency ratio of iclk is lower than that of pclk (or fclk), the subsequent bus access is started from the iclk cycle following the completion of the access to the peripheral functions. th erefore, the access cycles are described on an iclk basis. in the external bus control unit, the sum of the number of bu s cycles for internal main bus 1 and the number of divided clock synchronization cycles will be one cycle of bclk at a maximum. therefore, one bclk is added to the number of access cycles shown in table 4.1 . note 1. this applies to the number of cycles when the access from the cp u does not conflict with the instruction fetching to the external memory or bus access from the different bus master (dmaca or dtc).
r01ds0041ej0090 rev.0.90 page 63 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. table 4.1 list of i/o register s (address order) (1 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk 0008 0000h system mode monitor register mdmonr 16 16 3 iclk 0008 0002h system mode status register mdsr 16 16 3 iclk 0008 0006h system system control register 0 syscr0 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk 0008 0026h system system clock control register 3 sckcr3 16 16 3 iclk 0008 0028h system pll control register pllcr 16 16 3 iclk 0008 002ah system pll control register 2 pllcr2 8 8 3 iclk 0008 0030h system external bus clock control register bckcr 8 8 3 iclk 0008 0032h system main clock oscillator control register mosccr 8 8 3 iclk 0008 0033h system sub-clock oscillator control register sosccr 8 8 3 iclk 0008 0034h system low-speed clock oscillator control register lococr 8 8 3 iclk 0008 0035h system iwdt-dedicated low-speed clock oscillator control register ilococr 8 8 3 iclk 0008 0036h system high-speed clock oscillator control register hococr 8 8 3 iclk 0008 0037h system high-speed clock oscillator control register hococr2 8 8 3 iclk 0008 0040h system oscillation stop detection control register ostdcr 8 8 3 iclk 0008 0041h system oscillation stop detection status register ostdsr 8 8 3 iclk 0008 00a0h system operating power control register opccr 8 8 3 iclk 0008 00a1h system sleep mode return clock source switching register rstckcr 8 8 3 iclk 0008 00a2h system main clock oscillator wait control register moscwtcr 8 8 3 iclk 0008 00a3h system sub-clock oscillator wait control register soscwtcr 8 8 3 iclk 0008 00a6h system pll wait control register pllwtcr 8 8 3 iclk 0008 00a8h system loco wait control register 2 locowtcr2 8 8 3 iclk 0008 00a9h system hoco wait control register 2 hocowtcr2 8 8 3 iclk 0008 00c0h system reset status register 2 rstsr2 8 8 3 iclk 0008 00c2h system software reset register swrr 16 16 3 iclk 0008 00e0h system voltage monitoring 1 circuit/comparator a1 control register 1 lvd1cr1 8 8 3 iclk 0008 00e1h system voltage monitoring 1 circuit/comparator a1 status register lvd1sr 8 8 3 iclk 0008 00e2h system voltage monitoring 2 circuit/comparator a2 control register 1 lvd2cr1 8 8 3 iclk 0008 00e3h system voltage monitoring 2 circuit/comparator a2 status register lvd2sr 8 8 3 iclk 0008 03feh system protect register prcr 16 16 3 iclk 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2000h dmac0 dma source address register dmsar 32 32 2 iclk 0008 2004h dmac0 dma destination address register dmdar 32 32 2 iclk 0008 2008h dmac0 dma transfer count register dmcra 32 32 2 iclk 0008 200ch dmac0 dma block transfer count register dmcrb 16 16 2 iclk 0008 2010h dmac0 dma transfer mode register dmtmd 16 16 2 iclk 0008 2013h dmac0 dma interrupt setting register dmint 8 8 2 iclk 0008 2014h dmac0 dma address mode register dmamd 16 16 2 iclk 0008 2018h dmac0 dma offset register dmofr 32 32 2 iclk 0008 201ch dmac0 dma transfer enable register dmcnt 8 8 2 iclk 0008 201dh dmac0 dma software start register dmreq 8 8 2 iclk 0008 201eh dmac0 dma status register dmsts 8 8 2 iclk 000 8 201fh dmac0 dma activation source flag control register dmcsl 8 8 2 iclk
r01ds0041ej0090 rev.0.90 page 64 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 2040h dmac1 dma source address register dmsar 32 32 2 iclk 0008 2044h dmac1 dma destination address register dmdar 32 32 2 iclk 0008 2048h dmac1 dma transfer count register dmcra 32 32 2 iclk 0008 204ch dmac1 dma block transfer count register dmcrb 16 16 2 iclk 0008 2050h dmac1 dma transfer mode register dmtmd 16 16 2 iclk 0008 2053h dmac1 dma interrupt setting register dmint 8 8 2 iclk 0008 2054h dmac1 dma address mode register dmamd 16 16 2 iclk 0008 205ch dmac1 dma transfer enable register dmcnt 8 8 2 iclk 0008 205dh dmac1 dma software start register dmreq 8 8 2 iclk 0008 205eh dmac1 dma status register dmsts 8 8 2 iclk 0008 205fh dmac1 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2080h dmac2 dma source address register dmsar 32 32 2 iclk 0008 2084h dmac2 dma destination address register dmdar 32 32 2 iclk 0008 2088h dmac2 dma transfer count register dmcra 32 32 2 iclk 0008 208ch dmac2 dma block transfer count register dmcrb 16 16 2 iclk 0008 2090h dmac2 dma transfer mode register dmtmd 16 16 2 iclk 0008 2093h dmac2 dma interrupt setting register dmint 8 8 2 iclk 0008 2094h dmac2 dma address mode register dmamd 16 16 2 iclk 0008 209ch dmac2 dma transfer enable register dmcnt 8 8 2 iclk 0008 209dh dmac2 dma software start register dmreq 8 8 2 iclk 0008 209eh dmac2 dma status register dmsts 8 8 2 iclk 0008 209fh dmac2 dma activation source flag control register dmcsl 8 8 2 iclk 0008 20c0h dmac3 dma source address register dmsar 32 32 2 iclk 0008 20c4h dmac3 dma destination address register dmdar 32 32 2 iclk 0008 20c8h dmac3 dma transfer count register dmcra 32 32 2 iclk 0008 20cch dmac3 dma block transfer count register dmcrb 16 16 2 iclk 0008 20d0h dmac3 dma transfer mode register dmtmd 16 16 2 iclk 0008 20d3h dmac3 dma interrupt setting register dmint 8 8 2 iclk 0008 20d4h dmac3 dma address mode register dmamd 16 16 2 iclk 0008 20dch dmac3 dma transfer enable register dmcnt 8 8 2 iclk 0008 20ddh dmac3 dma software start register dmreq 8 8 2 iclk 0008 20deh dmac3 dma status register dmsts 8 8 2 iclk 0008 20dfh dmac3 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2200h dmac dmaca module activation register dmast 8 8 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk ? ? 0008 3002h bsc cs0 mode register cs0mod 16 16 1, 2 bclk ? ? 0008 3004h bsc cs0 wait control register 1 cs0wcr1 32 32 1, 2 bclk ? ? 0008 3008h bsc cs0 wait control register 2 cs0wcr2 32 32 1, 2 bclk ? ? 0008 3012h bsc cs1 mode register cs1mod 16 16 1, 2 bclk ? ? 0008 3014h bsc cs1 wait control register 1 cs1wcr1 32 32 1, 2 bclk ? ? 0008 3018h bsc cs1 wait control register 2 cs1wcr2 32 32 1, 2 bclk ? ? 0008 3022h bsc cs2 mode register cs2mod 16 16 1, 2 bclk ? ? 0008 3024h bsc cs2 wait control register 1 cs2wcr1 32 32 1, 2 bclk ? ? 0008 3028h bsc cs2 wait control register 2 cs2wcr2 32 32 1, 2 bclk ? ? 0008 3032h bsc cs3 mode register cs3mod 16 16 1, 2 bclk ? ? 0008 3034h bsc cs3 wait control register 1 cs3wcr1 32 32 1, 2 bclk ? ? 0008 3038h bsc cs3 wait control register 2 cs3wcr2 32 32 1, 2 bclk ? ? 0008 3802h bsc cs0 control register cs0cr 16 16 1, 2 bclk table 4.1 list of i/o register s (address order) (2 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 65 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. ? ? 0008 380ah bsc cs0 recovery cycle register cs0rec 16 16 1, 2 bclk ? ? 0008 3812h bsc cs1 control register cs1cr 16 16 1, 2 bclk ? ? 0008 381ah bsc cs1 recovery cycle register cs1rec 16 16 1, 2 bclk ? ? 0008 3822h bsc cs2 control register cs2cr 16 16 1, 2 bclk ? ? 0008 382ah bsc cs2 recovery cycle register cs2rec 16 16 1, 2 bclk ? ? 0008 3832h bsc cs3 control register cs3cr 16 16 1, 2 bclk ? ? 0008 383ah bsc cs3 recovery cycle register cs3rec 16 16 1, 2 bclk ? ? 0008 3880h bsc cs recovery cycle insertion enable register csrecen 16 16 1, 2 bclk 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk 0008 7015h icu interrupt request register 021 ir021 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7020h icu interrupt request register 032 ir032 8 8 2 iclk 0008 7021h icu interrupt request register 033 ir033 8 8 2 iclk 0008 7022h icu interrupt request register 034 ir034 8 8 2 iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk 0008 703ah icu interrupt request register 058 ir058 8 8 2 iclk 0008 703bh icu interrupt request register 059 ir059 8 8 2 iclk 0008 703fh icu interrupt request register 063 ir063 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk 0008 7058h icu interrupt request register 088 ir088 8 8 2 iclk 0008 7059h icu interrupt request register 089 ir089 8 8 2 iclk 0008 705ch icu interrupt request register 092 ir092 8 8 2 iclk 0008 705dh icu interrupt request register 093 ir093 8 8 2 iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2 iclk 0008 706ah icu interrupt request register 106 ir106 8 8 2 iclk 0008 706bh icu interrupt request register 107 ir107 8 8 2 iclk 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 000 8 707 ah icu interrupt request register 122 ir122 8 8 2 iclk table 4.1 list of i/o register s (address order) (3 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 66 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70c6h icu interrupt request register 198 ir198 8 8 2 iclk 0008 70c7h icu interrupt request register 199 ir199 8 8 2 iclk 0008 70c8h icu interrupt request register 200 ir200 8 8 2 iclk 0008 70c9h icu interrupt request register 201 ir201 8 8 2 iclk ? 0008 70d6h icu interrupt request register 214 ir214 8 8 2 iclk ? 0008 70d7h icu interrupt request register 215 ir215 8 8 2 iclk ? 0008 70d8h icu interrupt request register 216 ir216 8 8 2 iclk ? 0008 70d9h icu interrupt request register 217 ir217 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk 000 8 70e 4h icu interrupt request register 228 ir228 8 8 2 iclk table 4.1 list of i/o register s (address order) (4 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 67 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70e6h icu interrupt request register 230 ir230 8 8 2 iclk 0008 70e7h icu interrupt request register 231 ir231 8 8 2 iclk 0008 70e8h icu interrupt request register 232 ir232 8 8 2 iclk 0008 70e9h icu interrupt request register 233 ir233 8 8 2 iclk 0008 70eah icu interrupt request register 234 ir234 8 8 2 iclk 0008 70ebh icu interrupt request register 235 ir235 8 8 2 iclk 0008 70ech icu interrupt request register 236 ir236 8 8 2 iclk 0008 70edh icu interrupt request register 237 ir237 8 8 2 iclk 0008 70eeh icu interrupt request register 238 ir238 8 8 2 iclk 0008 70efh icu interrupt request register 239 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241 ir241 8 8 2 iclk 0008 70f2h icu interrupt request register 242 ir242 8 8 2 iclk 0008 70f3h icu interrupt request register 243 ir243 8 8 2 iclk 0008 70f4h icu interrupt request register 244 ir244 8 8 2 iclk 0008 70f5h icu interrupt request register 245 ir245 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 711bh icu dtc activation enable register027 dtcer027 8 8 2 iclk 0008 711ch icu dtc activation enable register028 dtcer028 8 8 2 iclk 0008 711dh icu dtc activation enable register029 dtcer029 8 8 2 iclk 0008 711eh icu dtc activation enable register030 dtcer030 8 8 2 iclk 0008 711fh icu dtc activation enable register031 dtcer031 8 8 2 iclk 0008 712dh icu dtc activation enable register045 dtcer045 8 8 2 iclk 0008 712eh icu dtc activation enable register046 dtcer046 8 8 2 iclk 0008 713ah icu dtc activation enable register058 dtcer058 8 8 2 iclk 0008 713bh icu dtc activation enable register059 dtcer059 8 8 2 iclk 0008 7140h icu dtc activation enable register064 dtcer064 8 8 2 iclk 0008 7141h icu dtc activation enable register065 dtcer065 8 8 2 iclk 0008 7142h icu dtc activation enable register066 dtcer066 8 8 2 iclk 0008 7143h icu dtc activation enable register067 dtcer067 8 8 2 iclk 0008 7144h icu dtc activation enable register068 dtcer068 8 8 2 iclk 0008 7145h icu dtc activation enable register069 dtcer069 8 8 2 iclk 0008 7146h icu dtc activation enable register070 dtcer070 8 8 2 iclk 0008 7147h icu dtc activation enable register071 dtcer071 8 8 2 iclk 0008 7166h icu dtc activation enable register102 dtcer102 8 8 2 iclk 0008 7167h icu dtc activation enable register103 dtcer103 8 8 2 iclk 0008 716ah icu dtc activation enable register106 dtcer106 8 8 2 iclk 0008 716bh icu dtc activation enable register107 dtcer107 8 8 2 iclk 0008 7172h icu dtc activation enable register114 dtcer114 8 8 2 iclk 0008 7173h icu dtc activation enable register115 dtcer115 8 8 2 iclk 0008 7174h icu dtc activation enable register116 dtcer116 8 8 2 iclk 0008 7175h icu dtc activation enable register117 dtcer117 8 8 2 iclk 0008 7179h icu dtc activation enable register121 dtcer121 8 8 2 iclk 0008 717ah icu dtc activation enable register122 dtcer122 8 8 2 iclk 0008 717dh icu dtc activation enable register125 dtcer125 8 8 2 iclk 0008 717eh icu dtc activation enable register126 dtcer126 8 8 2 iclk 0008 7181h icu dtc activation enable register129 dtcer129 8 8 2 iclk 0 0 08 7182h icu dtc activation enable register130 dtcer130 8 8 2 iclk table 4.1 list of i/o register s (address order) (5 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 68 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 7183h icu dtc activation enable register131 dtcer131 8 8 2 iclk 0008 7184h icu dtc activation enable register132 dtcer132 8 8 2 iclk 0008 7186h icu dtc activation enable register134 dtcer134 8 8 2 iclk 0008 7187h icu dtc activation enable register135 dtcer135 8 8 2 iclk 0008 7188h icu dtc activation enable register136 dtcer136 8 8 2 iclk 0008 7189h icu dtc activation enable register137 dtcer137 8 8 2 iclk 0008 718ah icu dtc activation enable register138 dtcer138 8 8 2 iclk 0008 718bh icu dtc activation enable register139 dtcer139 8 8 2 iclk 0008 718ch icu dtc activation enable register140 dtcer140 8 8 2 iclk 0008 718dh icu dtc activation enable register141 dtcer141 8 8 2 iclk 0008 71aeh icu dtc activation enable register174 dtcer174 8 8 2 iclk 0008 71afh icu dtc activation enable register175 dtcer175 8 8 2 iclk 0008 71b1h icu dtc activation enable register177 dtcer177 8 8 2 iclk 0008 71b2h icu dtc activation enable register178 dtcer178 8 8 2 iclk 0008 71b4h icu dtc activation enable register180 dtcer180 8 8 2 iclk 0008 71b5h icu dtc activation enable register181 dtcer181 8 8 2 iclk 0008 71b7h icu dtc activation enable register183 dtcer183 8 8 2 iclk 0008 71b8h icu dtc activation enable register184 dtcer184 8 8 2 iclk 0008 71c6h icu dtc activation enable register198 dtcer198 8 8 2 iclk 0008 71c7h icu dtc activation enable register199 dtcer199 8 8 2 iclk 0008 71c8h icu dtc activation enable register200 dtcer200 8 8 2 iclk 0008 71c9h icu dtc activation enable register201 dtcer201 8 8 2 iclk 0008 71d7h icu dtc activation enable register215 dtcer215 8 8 2 iclk 0008 71d8h icu dtc activation enable register216 dtcer216 8 8 2 iclk 0008 71dbh icu dtc activation enable register219 dtcer219 8 8 2 iclk 0008 71dch icu dtc activation enable register220 dtcer220 8 8 2 iclk 0008 71dfh icu dtc activation enable register223 dtcer223 8 8 2 iclk 0008 71e0h icu dtc activation enable register224 dtcer224 8 8 2 iclk 0008 71e3h icu dtc activation enable register227 dtcer227 8 8 2 iclk 0008 71e4h icu dtc activation enable register228 dtcer228 8 8 2 iclk 0008 71e7h icu dtc activation enable register231 dtcer231 8 8 2 iclk 0008 71e8h icu dtc activation enable register232 dtcer232 8 8 2 iclk 0008 71ebh icu dtc activation enable register235 dtcer235 8 8 2 iclk 0008 71ech icu dtc activation enable register236 dtcer236 8 8 2 iclk 0008 71efh icu dtc activation enable register239 dtcer239 8 8 2 iclk 0008 71f0h icu dtc activation enable register240 dtcer240 8 8 2 iclk 0008 71f7h icu dtc activation enable register247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc activation enable register248 dtcer248 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 000 8 721 5h icu interrupt request enable register 15 ier15 8 8 2 iclk table 4.1 list of i/o register s (address order) (6 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 69 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk 0008 7218h icu interrupt request enable register 18 ier18 8 8 2 iclk 0008 7219h icu interrupt request enable register 19 ier19 8 8 2 iclk 0008 721ah icu interrupt request enable register 1a ier1a 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 000 ipr000 8 8 3 iclk for reading, 2 iclk for writing 0008 7301h icu interrupt source priority register 001 ipr001 8 8 3 iclk for reading, 2 iclk for writing 0008 7302h icu interrupt source priority register 002 ipr002 8 8 3 iclk for reading, 2 iclk for writing 0008 7303h icu interrupt source priority register 003 ipr003 8 8 3 iclk for reading, 2 iclk for writing 0008 7304h icu interrupt source priority register 004 ipr004 8 8 3 iclk for reading, 2 iclk for writing 0008 7305h icu interrupt source priority register 005 ipr005 8 8 3 iclk for reading, 2 iclk for writing 0008 7306h icu interrupt source priority register 006 ipr006 8 8 3 iclk for reading, 2 iclk for writing 0008 7307h icu interrupt source priority register 007 ipr007 8 8 3 iclk for reading, 2 iclk for writing 0008 7320h icu interrupt source priority register 032 ipr032 8 8 3 iclk for reading, 2 iclk for writing 0008 7321h icu interrupt source priority register 033 ipr033 8 8 3 iclk for reading, 2 iclk for writing 0008 7322h icu interrupt source priority register 034 ipr034 8 8 3 iclk for reading, 2 iclk for writing 0008 732ch icu interrupt source priority register 044 ipr044 8 8 3 iclk for reading, 2 iclk for writing 0008 7339h icu interrupt source priority register 057 ipr057 8 8 3 iclk for reading, 2 iclk for writing 0008 733ah icu interrupt source priority register 058 ipr058 8 8 3 iclk for reading, 2 iclk for writing 0008 733bh icu interrupt source priority register 059 ipr059 8 8 3 iclk for reading, 2 iclk for writing 0008 733fh icu interrupt source priority register 063 ipr063 8 8 3 iclk for reading, 2 iclk for writing 0008 7340h icu interrupt source priority register 064 ipr064 8 8 3 iclk for reading, 2 iclk for writing 0008 7341h icu interrupt source priority register 065 ipr065 8 8 3 iclk for reading, 2 iclk for writing 0008 7342h icu interrupt source priority register 066 ipr066 8 8 3 iclk for reading, 2 iclk for writing 0008 7343h icu interrupt source priority register 067 ipr067 8 8 3 iclk for reading, 2 iclk for writing 0008 7344h icu interrupt source priority register 068 ipr068 8 8 3 iclk for reading, 2 iclk for writing 0008 7345h icu interrupt source priority register 069 ipr069 8 8 3 iclk for reading, 2 iclk for writing 0008 7346h icu interrupt source priority register 070 ipr070 8 8 3 iclk for reading, 2 iclk for writing 0008 7347h icu interrupt source priority register 071 ipr071 8 8 3 iclk for reading, 2 iclk for writing 0008 7358h icu interrupt source priority register 088 ipr088 8 8 3 iclk for reading, 2 iclk for writing table 4.1 list of i/o register s (address order) (7 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 70 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 7359h icu interrupt source priority register 089 ipr089 8 8 3 iclk for reading, 2 iclk for writing 0008 735ch icu interrupt source priority register 092 ipr092 8 8 3 iclk for reading, 2 iclk for writing 0008 735dh icu interrupt source priority register 093 ipr093 8 8 3 iclk for reading, 2 iclk for writing 0008 7366h icu interrupt source priority register 102 ipr102 8 8 3 iclk for reading, 2 iclk for writing 0008 7367h icu interrupt source priority register 103 ipr103 8 8 3 iclk for reading, 2 iclk for writing 0008 736ah icu interrupt source priority register 106 ipr106 8 8 3 iclk for reading, 2 iclk for writing 0008 736bh icu interrupt source priority register 107 ipr107 8 8 3 iclk for reading, 2 iclk for writing 0008 7372h icu interrupt source priority register 114 ipr114 8 8 3 iclk for reading, 2 iclk for writing 0008 7376h icu interrupt source priority register 118 ipr118 8 8 3 iclk for reading, 2 iclk for writing 0008 7379h icu interrupt source priority register 121 ipr121 8 8 3 iclk for reading, 2 iclk for writing 0008 737bh icu interrupt source priority register 123 ipr123 8 8 3 iclk for reading, 2 iclk for writing 0008 737dh icu interrupt source priority register 125 ipr125 8 8 3 iclk for reading, 2 iclk for writing 0008 737fh icu interrupt source priority register 127 ipr127 8 8 3 iclk for reading, 2 iclk for writing 0008 7381h icu interrupt source priority register 129 ipr129 8 8 3 iclk for reading, 2 iclk for writing 0008 7385h icu interrupt source priority register 133 ipr133 8 8 3 iclk for reading, 2 iclk for writing 0008 7386h icu interrupt source priority register 134 ipr134 8 8 3 iclk for reading, 2 iclk for writing 0008 738ah icu interrupt source priority register 138 ipr138 8 8 3 iclk for reading, 2 iclk for writing 0008 738bh icu interrupt source priority register 139 ipr139 8 8 3 iclk for reading, 2 iclk for writing 0008 73aah icu interrupt source priority register 170 ipr170 8 8 3 iclk for reading, 2 iclk for writing 0008 73abh icu interrupt source priority register 171 ipr171 8 8 3 iclk for reading, 2 iclk for writing 0008 73aeh icu interrupt source priority register 174 ipr174 8 8 3 iclk for reading, 2 iclk for writing 0008 73b1h icu interrupt source priority register 177 ipr177 8 8 3 iclk for reading, 2 iclk for writing 0008 73b4h icu interrupt source priority register 180 ipr180 8 8 3 iclk for reading, 2 iclk for writing 0008 73b7h icu interrupt source priority register 183 ipr183 8 8 3 iclk for reading, 2 iclk for writing 0008 73c6h icu interrupt source priority register 198 ipr198 8 8 3 iclk for reading, 2 iclk for writing 0008 73c7h icu interrupt source priority register 199 ipr199 8 8 3 iclk for reading, 2 iclk for writing 0008 73c8h icu interrupt source priority register 200 ipr200 8 8 3 iclk for reading, 2 iclk for writing 0008 73c9h icu interrupt source priority register 201 ipr201 8 8 3 iclk for reading, 2 iclk for writing 0008 73d6h icu interrupt source priority register 214 ipr214 8 8 3 iclk for reading, 2 iclk for writing 0008 73dah icu interrupt source priority register 218 ipr218 8 8 3 iclk for reading, 2 iclk for writing 0008 73deh icu interrupt source priority register 222 ipr222 8 8 3 iclk for reading, 2 iclk for writing 0008 73e2h icu interrupt source priority register 226 ipr226 8 8 3 iclk for reading, 2 iclk for writing 0008 73e6h icu interrupt source priority register 230 ipr230 8 8 3 iclk for reading, 2 iclk for writing table 4.1 list of i/o register s (address order) (8 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 71 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 73eah icu interrupt source priority register 234 ipr234 8 8 3 iclk for reading, 2 iclk for writing 0008 73eeh icu interrupt source priority register 238 ipr238 8 8 3 iclk for reading, 2 iclk for writing 0008 73f2h icu interrupt source priority register 242 ipr242 8 8 3 iclk for reading, 2 iclk for writing 0008 73f3h icu interrupt source priority register 243 ipr243 8 8 3 iclk for reading, 2 iclk for writing 0008 73f4h icu interrupt source priority register 244 ipr244 8 8 3 iclk for reading, 2 iclk for writing 0008 73f5h icu interrupt source priority register 245 ipr245 8 8 3 iclk for reading, 2 iclk for writing 0008 73f6h icu interrupt source priority register 246 ipr246 8 8 3 iclk for reading, 2 iclk for writing 0008 73f7h icu interrupt source priority register 247 ipr247 8 8 3 iclk for reading, 2 iclk for writing 0008 73f8h icu interrupt source priority register 248 ipr248 8 8 3 iclk for reading, 2 iclk for writing 0008 73f9h icu interrupt source priority register 249 ipr249 8 8 3 iclk for reading, 2 iclk for writing 0008 7400h icu dmaca activation request select register 0 dmrsr0 8 8 2 iclk 0008 7404h icu dmaca activation request select register 1 dmrsr1 8 8 2 iclk 0008 7408h icu dmaca activation request select register 2 dmrsr2 8 8 2 iclk 0008 740ch icu dmaca activation request select register 3 dmrsr3 8 8 2 iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2 iclk 0008 7507h icu irq control register 7 irqcr7 8 8 2 iclk 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk 0008 7514h icu irq pin digital filter setting registerr 0 irqfltc0 16 16 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2, 3 pclkb 2 iclk 0008 8002h cmt0 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 8004h cmt0 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 8006h cmt0 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8008h cmt1 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 800ah cmt1 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 800ch cmt1 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2, 3 pclkb 2 iclk 0008 8012h cmt2 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 8014h cmt2 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 8016h cmt2 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8018h cmt3 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 801ah cmt3 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 801ch cmt3 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8020h wdt wdt refresh register wdtrr 8 8 2, 3 pclkb 2 iclk 0008 8022h wdt wdt control register wdtcr 16 16 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (9 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 72 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 8024h wdt wdt status register wdtsr 16 16 2, 3 pclkb 2 iclk 0008 8026h wdt wdt reset control register wdtrcr 8 8 2, 3 pclkb 2 iclk 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2, 3 pclkb 2 iclk 0008 8032h iwdt iwdt control register iwdtcr 16 16 2, 3 pclkb 2 iclk 0008 8034h iwdt iwdt status register iwdtsr 16 16 2, 3 pclkb 2 iclk 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2, 3 pclkb 2 iclk 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2, 3 pclkb 2 iclk 0008 80c0h da d/a data register 0 dadr0 16 16 2, 3 pclkb 2 iclk 0008 80c2h da d/a data register 1 dadr1 16 16 2, 3 pclkb 2 iclk 0008 80c4h da d/a control register dacr 8 8 2, 3 pclkb 2 iclk 0008 80c5h da dadrm format select register dadpr 8 8 2, 3 pclkb 2 iclk 0008 8200h tmr0 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8201h tmr1 timer counter control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8202h tmr0 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8203h tmr1 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8204h tmr0 time constant register a tcora 8 8 2, 3 pclkb 2 iclk 0008 8205h tmr1 time constant register a tcora 8 8 2, 3 pclkb 2 iclk 0008 8206h tmr0 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk 0008 8207h tmr1 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk 0008 8208h tmr0 timer counter tcnt 8 8 2, 3 pclkb 2 iclk 0008 8209h tmr1 timer counter tcnt 8 8 2, 3 pclkb 2 iclk 0008 820ah tmr0 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk 0008 820bh tmr1 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk 0008 820ch tmr0 time count start register tcstr 8 8 2, 3 pclkb 2 iclk 0008 8210h tmr2 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8211h tmr3 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8212h tmr2 timer control/status registe tcsr 8 8 2, 3 pclkb 2 iclk 0008 8213h tmr3 timer control/status registe tcsr 8 8 2, 3 pclkb 2 iclk 0008 8214h tmr2 time constant register a tcora 8 8 2, 3 pclkb 2 iclk 0008 8215h tmr3 time constant register a tcora 8 8 2, 3 pclkb 2 iclk 0008 8216h tmr2 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk 0008 8217h tmr3 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk 0008 8218h tmr2 timer counter tcnt 8 8 2, 3 pclkb 2 iclk 0008 8219h tmr3 timer counter tcnt 8 8 2, 3 pclkb 2 iclk 0008 821ah tmr2 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk 0008 821bh tmr3 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk 0008 821ch tmr2 time count start register tcstr 8 8 2, 3 pclkb 2 iclk 0008 8280h crc crc control register crccr 8 8 2, 3 pclkb 2 iclk 0008 8281h crc crc data input register crcdir 8 8 2, 3 pclkb 2 iclk 0008 8282h crc crc data output register crcdor 16 16 2, 3 pclkb 2 iclk 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2, 3 pclkb 2 iclk 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2, 3 pclkb 2 iclk 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2, 3 pclkb 2 iclk 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2, 3 pclkb 2 iclk 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2, 3 pclkb 2 iclk 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2, 3 pclkb 2 iclk 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2, 3 pclkb 2 iclk 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2, 3 pclkb 2 iclk 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2, 3 pclkb 2 iclk 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2, 3 pclkb 2 iclk 0008 830ah riic0 slave address register l0 sarl0 8 8 2, 3 pclkb 2 iclk 0008 830bh riic0 slave address register u0 saru0 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (10 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 73 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 830ch riic0 slave address register l1 sarl1 8 8 2, 3 pclkb 2 iclk 0008 830dh riic0 slave address register u1 saru1 8 8 2, 3 pclkb 2 iclk 0008 830eh riic0 slave address register l2 sarl2 8 8 2, 3 pclkb 2 iclk 0008 830fh riic0 slave address register u2 saru2 8 8 2, 3 pclkb 2 iclk 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2, 3 pclkb 2 iclk 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2, 3 pclkb 2 iclk 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2, 3 pclkb 2 iclk 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2, 3 pclkb 2 iclk 0008 8380h rspi0 rspi control register spcr 8 8 2, 3 pclkb 2 iclk 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2, 3 pclkb 2 iclk 0008 8382h rspi0 rspi pin control register sppcr 8 8 2, 3 pclkb 2 iclk 0008 8383h rspi0 rspi status register spsr 8 8 2, 3 pclkb 2 iclk 0008 8384h rspi0 rspi data register spdr 32 16, 32 2, 3 pclkb 2 iclk 0008 8388h rspi0 rspi sequence control register spscr 8 8 2, 3 pclkb 2 iclk 0008 8389h rspi0 rspi sequence status register spssr 8 8 2, 3 pclkb 2 iclk 0008 838ah rspi0 rspi bit rate register spbr 8 8 2, 3 pclkb 2 iclk 0008 838bh rspi0 rspi data control register spdcr 8 8 2, 3 pclkb 2 iclk 0008 838ch rspi0 rspi clock delay register spckd 8 8 2, 3 pclkb 2 iclk 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2, 3 pclkb 2 iclk 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2, 3 pclkb 2 iclk 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2, 3 pclkb 2 iclk 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2, 3 pclkb 2 iclk 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2, 3 pclkb 2 iclk 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2, 3 pclkb 2 iclk 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2, 3 pclkb 2 iclk 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2, 3 pclkb 2 iclk 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2, 3 pclkb 2 iclk 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2, 3 pclkb 2 iclk 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2, 3 pclkb 2 iclk 0008 8600h mtu3 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8601h mtu4 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8602h mtu3 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8603h mtu4 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8604h mtu3 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8605h mtu3 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8606h mtu4 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8607h mtu4 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8608h mtu3 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8609h mtu4 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 860ah mtu timer output master enable register toer 8 8 2, 3 pclkb 2 iclk 0008 860dh mtu timer gate control register tgcr 8 8 2, 3 pclkb 2 iclk 0008 860eh mtu timer output control register 1 tocr1 8 8 2, 3 pclkb 2 iclk 0008 860fh mtu timer output control register 2 tocr2 8 8 2, 3 pclkb 2 iclk 0008 8610h mtu3 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8612h mtu4 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8614h mtu timer cycle data register tcdr 16 16 2, 3 pclkb 2 iclk 0008 8616h mtu timer dead time data register tddr 16 16 2, 3 pclkb 2 iclk 0008 8618h mtu3 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 861ah mtu3 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 861ch mtu4 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 861eh mtu4 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8620h mtu timer subcounter tcnts 16 16 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (11 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 74 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 8622h mtu timer cycle buffer re gister tcbr 16 16 2, 3 pclkb 2 iclk 0008 8624h mtu3 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 8626h mtu3 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 8628h mtu4 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 862ah mtu4 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 862ch mtu3 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 862dh mtu4 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8630h mtu timer interrupt skipping set register titcr 8 8 2, 3 pclkb 2 iclk 0008 8631h mtu timer interrupt skipping counter titcnt 8 8 2, 3 pclkb 2 iclk 0008 8632h mtu timer buffer transfer set register tbter 8 8 2, 3 pclkb 2 iclk 0008 8634h mtu timer dead time enable register tder 8 8 2, 3 pclkb 2 iclk 0008 8636h mtu timer output level buffer register tolbr 8 8 2, 3 pclkb 2 iclk 0008 8638h mtu3 timer buffer operation transfer mode register tbtm 8 8 2, 3 pclkb 2 iclk 0008 8639h mtu4 timer buffer operation transfer mode register tbtm 8 8 2, 3 pclkb 2 iclk 0008 8640h mtu4 timer a/d converter start request control register tadcr 16 16 2, 3 pclkb 2 iclk 0008 8644h mtu4 timer a/d converter start request cycle set register a tadcora 16 16 2, 3 pclkb 2 iclk 0008 8646h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 2, 3 pclkb 2 iclk 0008 8648h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16 2, 3 pclkb 2 iclk 0008 864ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 2, 3 pclkb 2 iclk 0008 8660h mtu timer waveform control register twcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8680h mtu timer start register tstr 8 8, 16 2, 3 pclkb 2 iclk 0008 8681h mtu timer synchronous register tsyr 8 8, 16 2, 3 pclkb 2 iclk 0008 8684h mtu timer read/write enable register trwer 8 8, 16 2, 3 pclkb 2 iclk 0008 8690h mtu0 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8691h mtu1 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8692h mtu2 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8693h mtu3 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8694h mtu4 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8695h mtu5 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8700h mtu0 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8701h mtu0 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8702h mtu0 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8703h mtu0 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8704h mtu0 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8705h mtu0 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8706h mtu0 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8708h mtu0 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 870ah mtu0 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 870ch mtu0 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 870eh mtu0 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 8720h mtu0 timer general register e tgre 16 16 2, 3 pclkb 2 iclk 0008 8722h mtu0 timer general register f tgrf 16 16 2, 3 pclkb 2 iclk 0008 8724h mtu0 timer interrupt enable register 2 tier2 8 8 2, 3 pclkb 2 iclk 0008 8726h mtu0 timer buffer operation transfer mode register tbtm 8 8 2, 3 pclkb 2 iclk 0008 8780h mtu1 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8781h mtu1 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8782h mtu1 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8784h mtu1 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8785h mtu1 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8786h mtu1 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 000 8 8788h mtu1 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 878ah mtu1 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (12 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 75 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 8790h mtu1 timer input capture control register ticcr 8 8 2, 3 pclkb 2 iclk 0008 8800h mtu2 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8801h mtu2 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8802h mtu2 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8804h mtu2 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8805h mtu2 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8806h mtu2 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8808h mtu2 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 880ah mtu2 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8880h mtu5 timer counter u tcntu 16 16 2, 3 pclkb 2 iclk 0008 8882h mtu5 timer general register u tgru 16 16 2, 3 pclkb 2 iclk 0008 8884h mtu5 timer control register u tcru 8 8 2, 3 pclkb 2 iclk 0008 8886h mtu5 timer i/o control register u tioru 8 8 2, 3 pclkb 2 iclk 0008 8890h mtu5 timer counter v tcntv 16 16 2, 3 pclkb 2 iclk 0008 8892h mtu5 timer general register v tgrv 16 16 2, 3 pclkb 2 iclk 0008 8894h mtu5 timer control register v tcrv 8 8 2, 3 pclkb 2 iclk 0008 8896h mtu5 timer i/o control register v tiorv 8 8 2, 3 pclkb 2 iclk 0008 88a0h mtu5 timer counter w tcntw 16 16 2, 3 pclkb 2 iclk 0008 88a2h mtu5 timer general register w tgrw 16 16 2, 3 pclkb 2 iclk 0008 88a4h mtu5 timer control register w tcrw 8 8 2, 3 pclkb 2 iclk 0008 88a6h mtu5 timer i/o control register w tiorw 8 8 2, 3 pclkb 2 iclk 0008 88b2h mtu5 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 88b4h mtu5 timer start registe tstr 8 8 2, 3 pclkb 2 iclk 0008 88b6h mtu5 timer compare match clear registe tcntcmpclr 8 8 2, 3 pclkb 2 iclk 0008 8900h poe input level control/status register 1 icsr1 16 8, 16 2, 3 pclkb 2 iclk 0008 8902h poe output level control/status register 1 ocsr1 16 8, 16 2, 3 pclkb 2 iclk 0008 8908h poe input level control/status register 2 icsr2 16 8, 16 2, 3 pclkb 2 iclk 0008 890ah poe software port output enable register spoer 8 8 2, 3 pclkb 2 iclk 0008 890bh poe port output enable control register 1 poecr1 8 8 2, 3 pclkb 2 iclk 0008 890ch poe port output enable control register 2 poecr2 8 8 2, 3 pclkb 2 iclk 0008 890eh poe input level control/status register 3 icsr3 16 8, 16 2, 3 pclkb 2 iclk 0008 9000h s12ad a/d control register adcsr 16 16 2, 3 pclkb 2 iclk 0008 9004h s12ad a/d channel select register a adansa 16 16 2, 3 pclkb 2 iclk 0008 9008h s12ad a/d-converted value addition mode select register adads 16 16 2, 3 pclkb 2 iclk 0008 900ch s12ad a/d-converted value addition count select register adadc 8 8 2, 3 pclkb 2 iclk 0008 900eh s12ad a/d control extended register adcer 16 16 2, 3 pclkb 2 iclk 0008 9010h s12ad a/d start trigger select register adstrgr 16 16 2, 3 pclkb 2 iclk 0008 9012h s12ad a/d-converted extended input control register adexicr 16 16 2, 3 pclkb 2 iclk 0008 9014h s12ad a/d channel select register b adansb 16 16 2, 3 pclkb 2 iclk 0008 9018h s12ad a/d double register addbldr 16 16 2, 3 pclkb 2 iclk 0008 901ah s12ad a/d temperature sensor data register adtsdr 16 16 2, 3 pclkb 2 iclk 0008 901ch s12ad a/d internal reference voltage data register adocdr 16 16 2, 3 pclkb 2 iclk 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2, 3 pclkb 2 iclk 0008 9020h s12ad a/d data register 0 addr0 16 16 2, 3 pclkb 2 iclk 0008 9022h s12ad a/d data register 1 addr1 16 16 2, 3 pclkb 2 iclk 0008 9024h s12ad a/d data register 2 addr2 16 16 2, 3 pclkb 2 iclk 0008 9026h s12ad a/d data register 3 addr3 16 16 2, 3 pclkb 2 iclk 0008 9028h s12ad a/d data register 4 addr4 16 16 2, 3 pclkb 2 iclk ? 0008 902ah s12ad a/d data register 5 addr5 16 16 2, 3 pclkb 2 iclk 0008 902ch s12ad a/d data register 6 addr6 16 16 2, 3 pclkb 2 iclk ? 0008 902eh s12ad a/d data register 7 addr7 16 16 2, 3 pclkb 2 iclk 0 0 08 9030h s12ad a/d data register 8 addr8 16 16 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (13 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 76 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 9032h s12ad a/d data register 9 addr9 16 16 2, 3 pclkb 2 iclk 0008 9034h s12ad a/d data register 10 addr10 16 16 2, 3 pclkb 2 iclk 0008 9036h s12ad a/d data register 11 addr11 16 16 2, 3 pclkb 2 iclk 0008 9038h s12ad a/d data register 12 addr12 16 16 2, 3 pclkb 2 iclk 0008 903ah s12ad a/d data register 13 addr13 16 16 2, 3 pclkb 2 iclk ? ? 0008 903ch s12ad a/d data register 14 addr14 16 16 2, 3 pclkb 2 iclk ? ? 0008 903eh s12ad a/d data register 15 addr15 16 16 2, 3 pclkb 2 iclk 0008 9060h s12ad a/d sampling state register 0 adsstr0 8 8 2, 3 pclkb 2 iclk 0008 9061h s12ad a/d sampling state register l adsstrl 8 8 2, 3 pclkb 2 iclk 0008 9066h s12ad a/d sample and hold circuit register adshcr 16 16 2, 3 pclkb 2 iclk 0008 9070h s12ad a/d sampling state register t adsstrt 8 8 2, 3 pclkb 2 iclk 0008 9071h s12ad a/d sampling state register o adsstro 8 8 2, 3 pclkb 2 iclk 0008 9073h s12ad a/d sampling state register 1 adsstr1 8 8 2, 3 pclkb 2 iclk 0008 9074h s12ad a/d sampling state register 2 adsstr2 8 8 2, 3 pclkb 2 iclk 0008 9075h s12ad a/d sampling state register 3 adsstr3 8 8 2, 3 pclkb 2 iclk 0008 9076h s12ad a/d sampling state register 4 adsstr4 8 8 2, 3 pclkb 2 iclk ? 0008 9077h s12ad a/d sampling state register 5 adsstr5 8 8 2, 3 pclkb 2 iclk 0008 9078h s12ad a/d sampling state register 6 adsstr6 8 8 2, 3 pclkb 2 iclk ? 0008 9079h s12ad a/d sampling state register 7 adsstr7 8 8 2, 3 pclkb 2 iclk 0008 907ah s12ad a/d disconnecting detection control register addiscr 8 8 2, 3 pclkb 2 iclk ? 0008 a000h sci0 serial mode register smr 8 8 2, 3 pclkb 2 iclk ? 0008 a001h sci0 bit rate register brr 8 8 2, 3 pclkb 2 iclk ? 0008 a002h sci0 serial control register scr 8 8 2, 3 pclkb 2 iclk ? 0008 a003h sci0 transmit data register tdr 8 8 2, 3 pclkb 2 iclk ? 0008 a004h sci0 serial status register ssr 8 8 2, 3 pclkb 2 iclk ? 0008 a005h sci0 receive data register rdr 8 8 2, 3 pclkb 2 iclk ? 0008 a006h sci0 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk ? 0008 a007h sci0 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk ? 0008 a008h sci0 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk ? 0008 a009h sci0 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk ? 0008 a00ah sci0 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk ? 0008 a00bh sci0 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk ? 0008 a00ch sci0 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk ? 0008 a00dh sci0 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a020h sci1 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a021h sci1 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a022h sci1 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a023h sci1 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a024h sci1 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a025h sci1 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a026h sci1 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a027h sci1 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a028h sci1 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a02ch sci1 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a02dh sci1 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a0a0h sci5 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a0a1h sci5 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a0a2h sci5 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a0a3h sci5 transmit data register tdr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (14 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 77 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 a0a4h sci5 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a0a5h sci5 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a0a6h sci5 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a0a7h sci5 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a0a8h sci5 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a0ach sci5 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a0adh sci5 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a0c0h sci6 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a0c1h sci6 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a0c2h sci6 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a0c3h sci6 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a0c4h sci6 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a0c5h sci6 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a0c6h sci6 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a0c7h sci6 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a0c8h sci6 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a0c9h sci6 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a0cah sci6 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a0cbh sci6 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a0cch sci6 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a0cdh sci6 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a100h sci8 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a101h sci8 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a102h sci8 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a103h sci8 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a104h sci8 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a105h sci8 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a106h sci8 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a107h sci8 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a108h sci8 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a109h sci8 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a10ah sci8 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a10bh sci8 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a10ch sci8 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a10dh sci8 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a120h sci9 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a121h sci9 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a122h sci9 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a123h sci9 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a124h sci9 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a125h sci9 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a126h sci9 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a127h sci9 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a128h sci9 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a129h sci9 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a12ah sci9 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a12bh sci9 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a12ch sci9 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a12dh sci9 spi mode register spmr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (15 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 78 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 b000h cac cac control register 0 cacr0 8 8 2, 3 pclkb 2 iclk 0008 b001h cac cac control register 1 cacr1 8 8 2, 3 pclkb 2 iclk 0008 b002h cac cac control register 2 cacr2 8 8 2, 3 pclkb 2 iclk 0008 b003h cac cac interrupt control register caicr 8 8 2, 3 pclkb 2 iclk 0008 b004h cac cac status register castr 8 8 2, 3 pclkb 2 iclk 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2, 3 pclkb 2 iclk 0008 b008h cac cac lower-limit value setting register callvr 16 16 2, 3 pclkb 2 iclk 0008 b00ah cac cac counter buffer register cacntbr 16 16 2, 3 pclkb 2 iclk 0008 b080h doc doc control register docr 8 8 2, 3 pclkb 2 iclk 0008 b082h doc doc data input register dodir 16 16 2, 3 pclkb 2 iclk 0008 b084h doc doc data setting register dodsr 16 16 2, 3 pclkb 2 iclk 0008 b100h elc event link control register elcr 8 8 2, 3 pclkb 2 iclk 0008 b102h elc event link setting register 1 elsr1 8 8 2, 3 pclkb 2 iclk 0008 b103h elc event link setting register 2 elsr2 8 8 2, 3 pclkb 2 iclk 0008 b104h elc event link setting register 3 elsr3 8 8 2, 3 pclkb 2 iclk 0008 b105h elc event link setting register 4 elsr4 8 8 2, 3 pclkb 2 iclk 0008 b108h elc event link setting register 7 elsr7 8 8 2, 3 pclkb 2 iclk 0008 b10bh elc event link setting register 10 elsr10 8 8 2, 3 pclkb 2 iclk 0008 b10dh elc event link setting register 12 elsr12 8 8 2, 3 pclkb 2 iclk 0008 b110h elc event link setting register 15 elsr15 8 8 2, 3 pclkb 2 iclk 0008 b111h elc event link setting register 16 elsr16 8 8 2, 3 pclkb 2 iclk 0008 b113h elc event link setting register 18 elsr18 8 8 2, 3 pclkb 2 iclk 0008 b114h elc event link setting register 19 elsr19 8 8 2, 3 pclkb 2 iclk 0008 b115h elc event link setting register 20 elsr20 8 8 2, 3 pclkb 2 iclk 0008 b116h elc event link setting register 21 elsr21 8 8 2, 3 pclkb 2 iclk 0008 b117h elc event link setting register 22 elsr22 8 8 2, 3 pclkb 2 iclk 0008 b118h elc event link setting register 23 elsr23 8 8 2, 3 pclkb 2 iclk 0008 b119h elc event link setting register 24 elsr24 8 8 2, 3 pclkb 2 iclk 0008 b11ah elc event link setting register 25 elsr25 8 8 2, 3 pclkb 2 iclk 0008 b11bh elc event link setting register 26 elsr26 8 8 2, 3 pclkb 2 iclk 0008 b11ch elc event link setting register 27 elsr27 8 8 2, 3 pclkb 2 iclk 0008 b11dh elc event link setting register 28 elsr28 8 8 2, 3 pclkb 2 iclk 0008 b11eh elc event link setting register 29 elsr29 8 8 2, 3 pclkb 2 iclk 0008 b11fh elc event link option setting register a elopa 8 8 2, 3 pclkb 2 iclk 0008 b120h elc event link option setting register b elopb 8 8 2, 3 pclkb 2 iclk 0008 b121h elc event link option setting register c elopc 8 8 2, 3 pclkb 2 iclk 0008 b122h elc event link option setting register d elopd 8 8 2, 3 pclkb 2 iclk 0008 b123h elc port group setting register 1 pgr1 8 8 2, 3 pclkb 2 iclk 0008 b124h elc port group setting register 2 pgr2 8 8 2, 3 pclkb 2 iclk 0008 b125h elc port group control register 1 pgc1 8 8 2, 3 pclkb 2 iclk 0008 b126h elc port group control register 2 pgc2 8 8 2, 3 pclkb 2 iclk 0008 b127h elc port buffer register 1 pdbf1 8 8 2, 3 pclkb 2 iclk 0008 b128h elc port buffer register 2 pdbf2 8 8 2, 3 pclkb 2 iclk 0008 b129h elc event link port setting register 0 pel0 8 8 2, 3 pclkb 2 iclk 0008 b12ah elc event link port setting register 1 pel1 8 8 2, 3 pclkb 2 iclk 0008 b12bh elc event link port setting register 2 pel2 8 8 2, 3 pclkb 2 iclk 0008 b12ch elc event link port setting register 3 pel3 8 8 2, 3 pclkb 2 iclk 0008 b12dh elc event link software event generation register elsegr 8 8 2, 3 pclkb 2 iclk 0008 b300h sci12 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 b301h sci12 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 b302h sci12 serial control register scr 8 8 2, 3 pclkb 2 iclk 000 8 b303h sci12 transmit data register tdr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (16 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 79 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 b304h sci12 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 b305h sci12 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 b306h sci12 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 b307h sci12 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 b308h sci12 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 b309h sci12 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 b30ah sci12 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 b30bh sci12 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 b30ch sci12 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 b30dh sci12 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 b320h sci12 extended serial mode enable register esmer 8 8 2, 3 pclkb 2 iclk 0008 b321h sci12 control register 0 cr0 8 8 2, 3 pclkb 2 iclk 0008 b322h sci12 control register 1 cr1 8 8 2, 3 pclkb 2 iclk 0008 b323h sci12 control register 2 cr2 8 8 2, 3 pclkb 2 iclk 0008 b324h sci12 control register 3 cr3 8 8 2, 3 pclkb 2 iclk 0008 b325h sci12 port control register pcr 8 8 2, 3 pclkb 2 iclk 0008 b326h sci12 interrupt control register icr 8 8 2, 3 pclkb 2 iclk 0008 b327h sci12 status register str 8 8 2, 3 pclkb 2 iclk 0008 b328h sci12 status clear register stcr 8 8 2, 3 pclkb 2 iclk 0008 b329h sci12 control field 0 data register cf0dr 8 8 2, 3 pclkb 2 iclk 0008 b32ah sci12 control field 0 compare enable register cf0cr 8 8 2, 3 pclkb 2 iclk 0008 b32bh sci12 control field 0 receive data register cf0rr 8 8 2, 3 pclkb 2 iclk 0008 b32ch sci12 primary control field 1 data register pcf1dr 8 8 2, 3 pclkb 2 iclk 0008 b32dh sci12 secondary control field 1 data register scf1dr 8 8 2, 3 pclkb 2 iclk 0008 b32eh sci12 control field 1 compare enable register cf1cr 8 8 2, 3 pclkb 2 iclk 0008 b32fh sci12 control field 1 receive data register cf1rr 8 8 2, 3 pclkb 2 iclk 0008 b330h sci12 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 b331h sci12 timer mode register tmr 8 8 2, 3 pclkb 2 iclk 0008 b332h sci12 timer prescaler register tpre 8 8 2, 3 pclkb 2 iclk 0008 b333h sci12 timer count register tcnt 8 8 2, 3 pclkb 2 iclk 0008 c000h port0 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c001h port1 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c002h port2 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c003h port3 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c004h port4 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c005h port5 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00ah porta port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00bh portb port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00ch portc port direction register pdr 8 8 2, 3 pclkb 2 iclk ? 0008 c00dh portd port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00eh porte port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c011h porth port direction register pdr 8 8 2, 3 pclkb 2 iclk ? 0008 c012h portj port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c020h port0 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c021h port1 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c022h port2 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c023h port3 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c024h port4 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c025h port5 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02ah porta port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02bh portb port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02ch portc port output data register podr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (17 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 80 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. ? 0008 c02dh portd port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02eh porte port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c031h porth port output data register podr 8 8 2, 3 pclkb 2 iclk ? 0008 c032h portj port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c040h port0 port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c041h port1 port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c042h port2 port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c043h port3 port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c044h port4 port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c045h port5 port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c04ah porta port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c04bh portb port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c04ch portc port input register pidr 8 8 2, 3 pclkb 2 iclk ? 0008 c04dh portd port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c04eh porte port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c051h porth port input register pidr 8 8 2, 3 pclkb 2 iclk ? 0008 c052h portj port input register pidr 8 8 2, 3 pclkb 2 iclk 0008 c060h port0 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c061h port1 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c062h port2 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c063h port3 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c064h port4 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c065h port5 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06ah porta port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06bh portb port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06ch portc port mode register pmr 8 8 2, 3 pclkb 2 iclk ? 0008 c06dh portd port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06eh porte port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c071h porth port mode register pmr 8 8 2, 3 pclkb 2 iclk ? 0008 c072h portj port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c082h port1 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c083h port1 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c084h port2 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c085h port2 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c086h port3 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c087h port3 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c094h porta open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c095h porta open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c096h portb open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c097h portb open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c098h portc open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c099h portc open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c09ch porte open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c09dh porte open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c0c0h port0 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c1h port1 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c2h port2 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c3h port3 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c4h port4 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c5h port5 pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cah porta pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 000 8 c0cbh portb pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (18 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 81 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 c0cch portc pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk ? 0008 c0cdh portd pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0ceh porte pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0d1h porth pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk ? 0008 c0d2h portj pull-up resistor control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0e1h port1 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e2h port2 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e3h port3 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e5h port5 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0eah porta drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0ebh portb drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0ech portc drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk ? 0008 c0edh portd drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0eeh porte drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0f1h porth drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk ? 0008 c0f2h portj drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk ? ? 0008 c100h mpc cs output enable register pfcse 8 8 2, 3 pclkb 2 iclk ? ? 0008 c104h mpc address output enable register 0 pfaoe0 8 8, 16 2, 3 pclkb 2 iclk ? ? 0008 c105h mpc address output enable register 1 pfaoe1 8 8, 16 2, 3 pclkb 2 iclk ? ? 0008 c106h mpc external bus control register 0 pfbcr0 8 8, 16 2, 3 pclkb 2 iclk ? ? 0008 c107h mpc external bus control register 1 pfbcr1 8 8, 16 2, 3 pclkb 2 iclk ? ? 0008 c11fh mpc write-protect register pwpr 8 8 2, 3 pclkb 2 iclk 0008 c143h mpc port 03 pin control select register p03pfs 8 8 2, 3 pclkb 2 iclk 0008 c145h mpc port 05 pin control select register p05pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c147h mpc port 07 pin control select register p07pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c14ah mpc port 12 pin control select register p12pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c14bh mpc port 13 pin control select register p13pfs 8 8 2, 3 pclkb 2 iclk 0008 c14ch mpc port 14 pin control select register p14pfs 8 8 2, 3 pclkb 2 iclk 0008 c14dh mpc port 15 pin control select register p15pfs 8 8 2, 3 pclkb 2 iclk 0008 c14eh mpc port 16 pin control select register p16pfs 8 8 2, 3 pclkb 2 iclk 0008 c14fh mpc port 17 pin control select register p17pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c150h mpc port 20 pin control select register p20pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c151h mpc port 21 pin control select register p21pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c152h mpc port 22 pin control select register p22pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c153h mpc port 23 pin control select register p23pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c154h mpc port 24 pin control select register p24pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c155h mpc port 25 pin control select register p25pfs 8 8 2, 3 pclkb 2 iclk 0008 c156h mpc port 26 pin control select register p26pfs 8 8 2, 3 pclkb 2 iclk 0008 c157h mpc port 27 pin control select register p27pfs 8 8 2, 3 pclkb 2 iclk 0008 c158h mpc port 30 pin control select register p30pfs 8 8 2, 3 pclkb 2 iclk 0008 c159h mpc port 31 pin control select register p31pfs 8 8 2, 3 pclkb 2 iclk 0008 c15ah mpc port 32 pin control select register p32pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c15bh mpc port 33 pin control select register p33pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c15ch mpc port 34 pin control select register p34pfs 8 8 2, 3 pclkb 2 iclk 0008 c160h mpc port 40 pin control select register p40pfs 8 8 2, 3 pclkb 2 iclk 0008 c161h mpc port 41 pin control select register p41pfs 8 8 2, 3 pclkb 2 iclk 0008 c162h mpc port 42 pin control select register p42pfs 8 8 2, 3 pclkb 2 iclk 0008 c163h mpc port 43 pin control select register p43pfs 8 8 2, 3 pclkb 2 iclk 0008 c164h mpc port 44 pin control select register p44pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c165h mpc port 45 pin control select register p45pfs 8 8 2, 3 pclkb 2 iclk 0008 c166h mpc port 46 pin control select register p46pfs 8 8 2, 3 pclkb 2 iclk ? 000 8 c167h mpc port 47 pin control select register p47pfs 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (19 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 82 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 c16ch mpc port 54 pin control select register p54pfs 8 8 2, 3 pclkb 2 iclk 0008 c16dh mpc port 55 pin control select register p55pfs 8 8 2, 3 pclkb 2 iclk 0008 c190h mpc port a0 pin control select register pa0pfs 8 8 2, 3 pclkb 2 iclk 0008 c191h mpc port a1 pin control select register pa1pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c192h mpc port a2 pin control select register pa2pfs 8 8 2, 3 pclkb 2 iclk 0008 c193h mpc port a3 pin control select register pa3pfs 8 8 2, 3 pclkb 2 iclk 0008 c194h mpc port a4 pin control select register pa4pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c195h mpc port a5 pin control select register pa5pfs 8 8 2, 3 pclkb 2 iclk 0008 c196h mpc port a6 pin control select register pa6pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c197h mpc port a7 pin control select register pa7pfs 8 8 2, 3 pclkb 2 iclk 0008 c198h mpc port b0 pin control select register pb0pfs 8 8 2, 3 pclkb 2 iclk 0008 c199h mpc port b1 pin control select register pb1pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c19ah mpc port b2 pin control select register pb2pfs 8 8 2, 3 pclkb 2 iclk 0008 c19bh mpc port b3 pin control select register pb3pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c19ch mpc port b4 pin control select register pb4pfs 8 8 2, 3 pclkb 2 iclk 0008 c19dh mpc port b5 pin control select register pb5pfs 8 8 2, 3 pclkb 2 iclk 0008 c19eh mpc port b6 pin control select register pb6pfs 8 8 2, 3 pclkb 2 iclk 0008 c19fh mpc port b7 pin control select register pb7pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1a0h mpc port c0 pin control select register pc0pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1a1h mpc port c1 pin control select register pc1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a2h mpc port c2 pin control select register pc2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a3h mpc port c3 pin control select register pc3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a4h mpc port c4 pin control select register pc4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a5h mpc port c5 pin control select register pc5pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a6h mpc port c6 pin control select register pc6pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a7h mpc port c7 pin control select register pc7pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c1a8h mpc port d0 pin control select register pd0pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c1a9h mpc port d1 pin control select register pd1pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c1aah mpc port d2 pin control select register pd2pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1abh mpc port d3 pin control select register pd3pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1ach mpc port d4 pin control select register pd4pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1adh mpc port d5 pin control select register pd5pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1aeh mpc port d6 pin control select register pd6pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1afh mpc port d7 pin control select register pd7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b0h mpc port e0 pin control select register pe0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b1h mpc port e1 pin control select register pe1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b2h mpc port e2 pin control select register pe2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b3h mpc port e3 pin control select register pe3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b4h mpc port e4 pin control select register pe4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b5h mpc port e5 pin control select register pe5pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1b6h mpc port e6 pin control select register pe6pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1b7h mpc port e7 pin control select register pe7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1c8h mpc port h0 pin control select register ph0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1c9h mpc port h1 pin control select register ph1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1cah mpc port h2 pin control select register ph2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1cbh mpc port h3 pin control select register ph3pfs 8 8 2, 3 pclkb 2 iclk ? 0008 c1d1h mpc port j1 pin control select register pj1pfs 8 8 2, 3 pclkb 2 iclk ? ? 0008 c1d3h mpc port j3 pin control select register pj3pfs 8 8 2, 3 pclkb 2 iclk 0008 c280h system deep standby control register dpsbycr 8 8 4, 5 pclkb 2, 3 iclk 0008 c282h system deep standby interrupt enable register 0 dpsier0 8 8 4, 5 pclkb 2, 3 iclk 0008 c284h system deep standby interrupt enable register 2 dpsier2 8 8 4, 5 pclkb 2, 3 iclk 000 8 c286h system deep standby interrupt flag register 0 dpsifr0 8 8 4, 5 pclkb 2, 3 iclk table 4.1 list of i/o register s (address order) (20 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 83 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 c288h system deep standby interrupt flag register 2 dpsifr2 8 8 4, 5 pclkb 2, 3 iclk 0008 c28ah system deep standby interrupt edge register 0 dpsiegr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c28ch system deep standby interrupt edge register 2 dpsiegr2 8 8 4, 5 pclkb 2, 3 iclk 0008 c28fh system flash hoco software standy control register fhssbycr 8 8 4, 5 pclkb 2, 3 iclk 0008 c290h system reset status register 0 rstsr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c291h system reset status register 1 rstsr1 8 8 4, 5 pclkb 2, 3 iclk 0008 c293h system main clock oscillator forced oscillation control register mofcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c294h system high-speed clock oscillator power supply control register hocopcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c296h flash flash write erase protection register fwepror 8 8 4, 5 pclkb 2, 3 iclk 0008 c297h system voltage monitoring circuit/comparator a control register lvcmpcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c298h system voltage detection level select register lvdlvlr 8 8 4, 5 pclkb 2, 3 iclk 0008 c29ah system voltage monitoring 1 circuit/comparator a1 control register 0 lvd1cr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c29bh system voltage monitoring 2 circuit/comparator a2 control register 0 lvd2cr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c2a0h to 0008 c2bfh system deep standby backup register 0 to 31 dpsbkr0 to dpsbkr31 8 8 4, 5 pclkb 2, 3 iclk 0008 c400h rtc 64-hz counter r64cnt 8 8 2, 3 pclkb 2 iclk 0008 c402h rtc second counter rseccnt 8 8 2, 3 pclkb 2 iclk 0008 c404h rtc minute counter rmincnt 8 8 2, 3 pclkb 2 iclk 0008 c406h rtc hour counter rhrcnt 8 8 2, 3 pclkb 2 iclk 0008 c408h rtc day-of-week counter rwkcnt 8 8 2, 3 pclkb 2 iclk 0008 c40ah rtc date counter rdaycnt 8 8 2, 3 pclkb 2 iclk 0008 c40ch rtc month counter rmoncnt 8 8 2, 3 pclkb 2 iclk 0008 c40eh rtc year counter ryrcnt 16 16 2, 3 pclkb 2 iclk 0008 c410h rtc second alarm register rsecar 8 8 2, 3 pclkb 2 iclk 0008 c412h rtc minute alarm register rminar 8 8 2, 3 pclkb 2 iclk 0008 c414h rtc hour alarm register rhrar 8 8 2, 3 pclkb 2 iclk 0008 c416h rtc day-of-week alarm register rwkar 8 8 2, 3 pclkb 2 iclk 0008 c418h rtc date alarm register rdayar 8 8 2, 3 pclkb 2 iclk 0008 c41ah rtc month alarm register rmonar 8 8 2, 3 pclkb 2 iclk 0008 c41ch rtc year alarm register ryrar 16 16 2, 3 pclkb 2 iclk 0008 c41eh rtc year alarm enable register ryraren 8 8 2, 3 pclkb 2 iclk 0008 c422h rtc rtc control register 1 rcr1 8 8 2, 3 pclkb 2 iclk 0008 c424h rtc rtc control register 2 rcr2 8 8 2, 3 pclkb 2 iclk 0008 c426h rtc rtc control register 3 rcr3 8 8 2, 3 pclkb 2 iclk 0008 c42eh rtc time error adjustment register radj 8 8 2, 3 pclkb 2 iclk 0008 c440h rtc time capture control register 0 rtccr0 8 8 2, 3 pclkb 2 iclk 0008 c442h rtc time capture control register 1 rtccr1 8 8 2, 3 pclkb 2 iclk 0008 c444h rtc time capture control register 2 rtccr2 8 8 2, 3 pclkb 2 iclk 0008 c452h rtc second capture register 0 rseccp0 8 8 2, 3 pclkb 2 iclk 0008 c454h rtc minute capture register 0 rmincp0 8 8 2, 3 pclkb 2 iclk 0008 c456h rtc hour capture register 0 rhrcp0 8 8 2, 3 pclkb 2 iclk 0008 c45ah rtc date capture register 0 rdaycp0 8 8 2, 3 pclkb 2 iclk 0008 c45ch rtc month capture register 0 rmoncp0 8 8 2, 3 pclkb 2 iclk 0008 c462h rtc second capture register 1 rseccp1 8 8 2, 3 pclkb 2 iclk 0008 c464h rtc minute capture register 1 rmincp1 8 8 2, 3 pclkb 2 iclk 0008 c466h rtc hour capture register 1 rhrcp1 8 8 2, 3 pclkb 2 iclk 0008 c46ah rtc date capture register 1 rdaycp1 8 8 2, 3 pclkb 2 iclk 0008 c46ch rtc month capture register 1 rmoncp1 8 8 2, 3 pclkb 2 iclk 0008 c472h rtc second capture register 2 rseccp2 8 8 2, 3 pclkb 2 iclk 0008 c474h rtc minute capture register 2 rmincp2 8 8 2, 3 pclkb 2 iclk 0 0 08 c476h rtc hour capture register 2 rhrcp2 8 8 2, 3 pclkb 2 iclk 0008 c47ah rtc date capture register 2 rdaycp2 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (21 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 84 of 144 aug 10, 2011 rx210 group 4. i/o registers under development preliminary document specifications in this document are tentative and subject to change. 0008 c47ch rtc month capture register 2 rmoncp2 8 8 2, 3 pclkb 2 iclk 0008 c500h temps temperature sensor control register tscr 8 8 2, 3 pclkb 2 iclk 0008 c580h cmpb comparator b control register 1 cpbcnt1 8 8 2, 3 pclkb 2 iclk 0008 c582h cmpb comparator b flag register cpbflg 8 8 2, 3 pclkb 2 iclk 0008 c583h cmpb comparator b interrupt control register cpbint 8 8 2, 3 pclkb 2 iclk 0008 c584h cmpb comparator b filter select register cpbf 8 8 2, 3 pclkb 2 iclk 007f c402h flash flash mode register fmodr 8 8 2, 3 fclk 2 iclk 007f c410h flash flash access status register fastat 8 8 2, 3 fclk 2 iclk 007f c411h flash flash access error interrupt enable register faeint 8 8 2, 3 fclk 2 iclk 007f c412h flash flash ready interrupt enable register frdyie 8 8 2, 3 fclk 2 iclk 007f c440h flash e2 data flash read enable register 0 dflre0 16 16 2, 3 fclk 2 iclk 007f c450h flash e2 data flash programming/erasure enable register 0 dflwe0 16 16 2, 3 fclk 2 iclk 007f c454h flash fcu ram enable register fcurame 16 16 2, 3 fclk 2 iclk 007f ffb0h flash flash status register 0 fstatr0 8 8 2, 3 fclk 2 iclk 007f ffb1h flash flash status register 1 fstatr1 8 8 2, 3 fclk 2 iclk 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2, 3 fclk 2 iclk 007f ffb4h flash flash protection register fprotr 16 16 2, 3 fclk 2 iclk 007f ffb6h flash flash reset register fresetr 16 16 2, 3 fclk 2 iclk 007f ffbah flash fcu command register fcmdr 16 16 2, 3 fclk 2 iclk 007f ffc8h flash fcu processing switching register fcpsr 16 16 2, 3 fclk 2 iclk 007f ffcah flash e2 data flash blank check control register dflbccnt 16 16 2, 3 fclk 2 iclk 007f ffcch flash flash p/e status register fpestat 16 16 2, 3 fclk 2 iclk 007f ffceh flash e2 data flash blank check status register dflbcstat 16 16 2, 3 fclk 2 iclk 007f ffe8h flash peripheral clock notification register pckar 16 16 2, 3 fclk 2 iclk table 4.1 list of i/o register s (address order) (22 / 22) 100-pin 80-pin 64-pin address module symbol register name register symbol number of bits access size number of access states iclk ? pclk iclk < pclk
r01ds0041ej0090 rev.0.90 page 85 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. note 1. ports12, 13, 16 and 17 are 5 v tolerant. note 2. connect avcc0 to vcc. when neither the a/d converter nor the d/a converter is in us e, do not leave the avcc0, refh/ vrefh0, avss0, and vrefl/vrefl0 pins open. connect the avcc0 and vrefh/vrefh0 pins to vcc, and the avss0 and vrefl/vrefl0 pins to vss, respectively. table 5.1 absolute maximum ratings conditions: vss = avss0 = vrefl = vrefl0 = 0v item symbol value unit power supply voltage vcc ?0.3 to +6.5 v input voltage (except for ports for 5 v tolerant* 1 )v in ?0.3 to vcc + 0.3 v input voltage (ports for 5 v tolerant* 1 )v in ?0.3 to +6.5 v reference power supply voltage vrefh, vrefh0 ?0.3 to vcc + 0.3 v analog power supply voltage avcc0* 2 ?0.3 to +6.5 v analog input voltage v an ?0.3 to vcc + 0.3 v operating temperature t opr ?40 to +85 c storage temperature t stg ?55 to +125 c
r01ds0041ej0090 rev.0.90 page 86 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.2 dc characteristics note 1. this does not include the pins which are multiplexed as ports for 5 v tolerant. note 2. pins 12, 13, 16 and 17 are for 5 v tolerant. table 5.2 dc characteristics (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0v t a = ?40 to +85c item symbol min. typ. max. unit test conditions schmitt trigger input voltage irq input pin* 1 mtu input pin* 1 tmr input pin* 1 sci input pin* 1 adtrg0# input pin* 1 res#, nmi v ih vcc 0.8 ? vcc + 0.3 v v il ?0.3 ? vcc 0.2 ? v t vcc 0.1 ? ? riic input pin (except for smbus) v ih vcc 0.7 ? 5.8 v il ?0.3 ? vcc 0.3 ? v t vcc 0.05 ? ? ports for 5 v tolerant* 2 v ih vcc 0.8 ? 5.8 v il ?0.3 ? vcc 0.2 other input pins excluding ports for 5 v tolerant v ih vcc 0.8 ? vcc + 0.3 v il ?0.3 ? vcc 0.2 input high voltage (except for schmitt trigger input pin) md pin v ih vcc 0.9 ? vcc + 0.3 v extal, rspi, wait#, tck vcc 0.8 ? vcc + 0.3 xcin vcc 0.8 ? vcc + 0.3 d0 to d15 vcc 0.7 ? vcc + 0.3 riic (smbus) 2.1 ? vcc + 0.3 input low voltage (except for schmitt trigger input pin) md pin, emle v il ?0.3 ? vcc 0.1 v extal, rspi, wait#, tck ?0.3 ? vcc 0.2 xcin ?0.3 ? vcc 0.2 d0 to d15 ?0.3 ? vcc 0.3 riic (smbus) ?0.3 ? 0.8
r01ds0041ej0090 rev.0.90 page 87 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. this does not include the pins which are multiplexed as ports for 5 v tolerant. note 2. pins 12, 13, 16 and 17 are for 5 v tolerant. table 5.3 dc characteristics (2) conditions: vcc = avcc0 = 1.62 to 2.7 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol min. typ. max. unit test conditions schmitt trigger input voltage irq input pin* 1 mtu input pin* 1 tmr input pin* 1 sci input pin* 1 adtrg0# input pin* 1 res#, nmi v ih vcc 0.8 ? vcc + 0.3 v v il ?0.3 ? vcc 0.2 ports for 5 v tolerant* 2 v ih vcc 0.8 ? 5.8 v il ?0.3 ? vcc 0.2 other input pins excluding ports for 5 v tolerant v ih vcc 0.8 ? vcc + 0.3 v il ?0.3 ? vcc 0.2 input high voltage (except for schmitt trigger input pin) md pin v ih vcc 0.9 ? vcc + 0.3 v extal, rspi, wait#, tck vcc 0.8 ? vcc + 0.3 xcin vcc 0.8 ? vcc + 0.3 d0 to d15 vcc 0.7 ? vcc + 0.3 input low voltage (except for schmitt trigger input pin) md pin v il ?0.3 ? vcc 0.1 v extal, rspi, wait#, tck ?0.3 ? vcc 0.2 xcin ?0.3 ? vcc 0.2 d0 to d15 ?0.3 ? vcc 0.3 table 5.4 dc characteristics (3) conditions: vcc = avcc0 = 1.62 to 2.7 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol min. typ. max. unit test conditions input leakage current res#, md pin, nmi ? i in ? ??1.0av in = 0 v, v in = vcc three - state leakage current (off-state) other than ports for 5 v tolerant ? i tsi ? ??0.2av in = 0 v, v in = vcc v in = 0 v, 5.8v ports for 5 v tolerant ? ? t.b.d input capacitance all input pins (except for ports 12, 13, 16, 17, port 4, and port e) c in ? ? 15 pf v in = 0 v, f = 1 mhz, t a = 25c ports 12, 13, 16, 17, port 4, and port e ? ? t.b.d table 5.5 dc characteristics (4) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = av ss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol vcc. unit test conditions 1.62 to 2.7 v 2.7 to 4.0 v 4.0 to 5.5 v input pull-up mos current all ports (except for port 35) ?i p 5 to 150 10 to 200 50 to 400 a v in = 0 v
r01ds0041ej0090 rev.0.90 page 88 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. supply current values are with all output pins unloaded and all input pull-up moss in the off state. note 2. measured with clocks suppl ied to the peripheral functions. this does not include the bgo operation. note 3. measured with clocks not supplied to the peripheral functions. this does not include the bgo operation. note 4. the values are for reference. note 5. this is the increase in current drawn if data are written to or erased from the rom or the flash memory for data storage during program execution. note 6. this is the value when vcc = 3.3 v note 1. the reference power supply current is included in the power supply current value for d/a conversion. table 5.6 dc characteristics (5) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = 0 v, t a = ?40 to +85c item symbol typ.* 6 max. unit test conditions current drawn* 1 high-speed operating mode max. operation* 2 i cc ? t.b.d ma iclk = 50 mhz pclkb = 25 mhz fclk = 25 mhz bclk = 25 mhz normal operation* 3 t. b . d ? medium-speed operating modes a and b max. operation* 2 ? t.b.d iclk = 32 mhz pclkb = 32 mhz fclk = 32 mhz bclk = 16 mhz normal operation* 3 t. b . d ? sleep mode t.b.d t.b.d all module clock stop mode* 4 t. b . d t. b . d increase during bgo* 5 medium-speed operating mode a t. b . d ? medium-speed operating mode b t. b . d ? low-speed operating mode 1 max. operation* 2 ? t.b.d iclk = 1 mhz normal operation* 3 t. b . d ? low-speed operating mode 2 max. operation* 2 ? t.b.d iclk = 32 khz normal operation* 3 t. b . d ? sotware standby rtc stop t.b.d t.b.d a rtc operation t.b.d t.b.d deep software standby rtc stop t.b.d t.b.d rtc operation t.b.d t.b.d table 5.7 dc characteristics (6) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions analog power supply current* 1 during a/d conversion ai cc ?t.b.dt.b.dma during d/a conversion (per channel) ? t.b.d t.b.d temperature sensor ? t.b.d t.b.d a waiting for a/d, d/a conversion (all units) ? t.b.d t.b.d a/d, d/a converter in standby mode (all units) ? t.b.d t.b.d reference power supply current during a/d conversion i refh , i refh0 ?t.b.dt.b.dma during d/a conversion (per channel) ? t.b.d t.b.d waiting for a/d, d/a conversion (all units) ? t.b.d t.b.d a a/d, d/a converter in standby mode (all units) ? t.b.d t.b.d
r01ds0041ej0090 rev.0.90 page 89 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. table 5.8 dc characteristics (7) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol min. typ. max. unit vcc rising gradient srvcc 0.02 ? 20 ms/v vcc falling gradient sfvcc 0.02 ? 20 ms/v table 5.9 permissible output currents conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol max. unit permissible output low current (average value per pin) all output pins when the driving ability is low i ol 4.0 ma when the driving ability is high 8.0 permissible output low current (max. value per pin) all output pins when the dr iving ability is low 4.0 ma when the driving ability is high 8.0 permissible output low current (total) total of all output pins ? i ol 80 ma permissible output high current (average value per pin) all output pins when the dr iving ability is low ?i oh 4.0 ma when the driving ability is high 8.0 permissible output high current (max. value per pin) all output pins when the dr iving ability is low 4.0 ma when the driving ability is high 8.0 permissible output high current (total) total of all output pins ? ?i oh 80 ma table 5.10 output values of current and voltage conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = av ss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol vcc. unit 1.62 to 2.7 v 2.7 to 4.0 v 4.0 to 5.5 v output low all output pins (except for riic pins) when the driving ability is low i ol /v ol 0.5 ma/0.4 v 3.0 ma/1.0 v 4.0 ma/1.0 v ma/v when the driving ability is high 1.0 ma/0.4 v 5.0 ma/1.0 v 8.0 ma/1.0 v riic pins standard, fm ? 3.0 ma/0.4 v 3.0 ma/0.4 v fm ? 6.0 ma/0.6 v 6.0 ma/0.6 v output high all output pins when the driving ability is low ?i oh /v oh 0.5 ma/vcc?0.4 v 3.0 ma/vcc?1.0 v 4.0 ma/vcc?1.0 v ma/v when the driving ability is high 1.0 ma/vcc?0.4 v 5.0 ma/vcc?1.0 v 8.0 ma/vcc?1.0 v
r01ds0041ej0090 rev.0.90 page 90 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.3 ac characteristics note 1. the fclk must be running at a frequency of at least 4 mhz during programming or erasing of the flash memory. note 1. the vcc is 2.7 to 5.5 v and the fclk must be running at a frequency of at least 4 mhz duri ng programming or erasing of t he flash memory. note 1. the vcc is 1.62 to 3.6 v and the fclk must be running at a frequency of at least 4 mhz during programming or erasing of the flash memory. table 5.11 operation frequency value (high-speed operating mode) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol vcc. unit 2.7 to 4.0 v maximum operating frequency system clock (iclk) f max 50 mhz flashif clock (fclk)* 1 32 peripheral module clock (pclkb) 32 peripheral module clock (pclk) 50 external bus clock (bclk) 25 bclk pin output 12.5 table 5.12 operation frequency value (medium-speed operating mode a) conditions: vcc = avcc0 = 1.62 to 5.5v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol vcc. unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 20 32 32 mhz flashif clock (fclk)* 1 20 32 32 peripheral module clock (pclkb) 20 32 32 peripheral module clock (pclk) 20 32 32 external bus clock (bclk) 12 16 16 bclk pin output 6 8 8 table 5.13 operation frequency value (medium-speed operating mode b) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol vcc. unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 20 32 32 mhz flashif clock (fclk)* 1 20 32 32 peripheral module clock (pclkb) 20 32 32 peripheral module clock (pclk) 20 32 32 external bus clock (bclk) 12 16 16 bclk pin output 6 8 8
r01ds0041ej0090 rev.0.90 page 91 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. programming and erasing the flash memory is impossible. note 1. programming and erasing the flash memory is impossible. note 2. accuracy of a/d conversion is not guaranteed. table 5.14 operation frequency value (low-speed operating mode 1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol vcc. unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 111m h z flashif clock (fclk)* 1 111 peripheral module clock (pclkb) 1 1 1 peripheral module clock (pclk) 1 1 1 external bus clock (bclk) 1 1 1 bclk pin output 1 1 1 table 5.15 operation frequency value (low-speed operating mode 2) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl=vrefl0 = 0v t a = ?40 to +85c item symbol vcc. unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 32 32 32 mhz flashif clock (fclk)* 1 32 32 32 peripheral module clock (pclkb) 32 32 32 peripheral module clock (pclk)* 2 32 32 32 external bus clock (bclk) 32 32 32 bclk pin output 32 32 32
r01ds0041ej0090 rev.0.90 page 92 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.4 clock timing note: ? set high driving ability for the output port pin to be used for the bclk pin function. table 5.16 clock timing (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = 1.8 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v bclk = up to 25 mhz (bclk output = up to 12.5 mhz), t a = ?40 to +85c item symbol min. typ. max. unit test conditions bclk pin output cycle time t bcyc 80 ? ? ns figure 5.1 bclk pin output high pulse width t ch 20 ? ? ns bclk pin output low pulse width t cl 20 ? ? ns bclk pin output rising time t cr ? ? 15 ns bclk pin output falling time t cr ? ? 15 ns table 5.17 clock timing (2) conditions: vcc = avcc0 = 1.8 to 2.7 v, vrefh=vrefh0 = 1.8 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v bclk = up to 16 mhz (bcl k output = up to 8 mhz), t a = ?40 to +85c item symbol min. typ. max. unit test conditions bclk pin output cycle time t bcyc 125 ? ? ns figure 5.1 bclk pin output high pulse width t ch 30 ? ? ns bclk pin output low pulse width t cl 30 ? ? ns bclk pin output rising time t cr ? ? 25 ns bclk pin output falling time t cr ? ? 25 ns table 5.18 clock timing (3) conditions: vcc = avcc0 = 1.62 to 1.8 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl=vrefl0 = 0 v bclk = up to 12 mhz (bcl k output = up to 6 mhz), t a = ?40 to +85c item symbol min. typ. max. unit test conditions bclk pin output cycle time t bcyc 167 ? ? ns figure 5.1 bclk pin output high pulse width t ch 42 ? ? ns bclk pin output low pulse width t cl 42 ? ? ns bclk pin output rising time t cr ? ? 35 ns bclk pin output falling time t cr ? ? 35 ns
r01ds0041ej0090 rev.0.90 page 93 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. table 5.19 clock timing (4) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol min. typ. max. unit test conditions extal external clock input cycle time t excyc 50 ? ? ns figure 5.2 extal external clock input high pulse width t exh 20 ? ? ns extal external clock input low pulse width t exl 20 ? ? ns extal external clock rising time t exr ?? 5ns extal external clock falling time t exf ?? 5ns extal external clock input wait time t exwt 1??ms main clock oscillator oscillation frequency f main 1?20mhz main clock oscillation settling time (crystal) t mainosc t.b.d ? ? ms figure 5.3 main clock oscillation settl ing wait time (crystal) t mainoscwt t.b.d ? ? ms low-speed clock cycle time t cyc 8.89 8 7.27 s low-speed clock oscillator oscillation frequency f loco 112.5 125 137.5 khz low-speed clock oscillati on settling wait time t locowt ? ? 20 s figure 5.4 high-speed clock oscillator oscillation frequency f hoco t.b.d 32 t.b.d mhz hcfrq = 00b t.b.d 36.864 t.b.d hcfrq = 01b t.b.d 40 t.b.d hcfrq = 10b t.b.d 50 t.b.d hcfrq = 11b high-speed clock oscillation settling wait time 1 t hocowt1 ? ? t.b.d ms figure 5.5 high-speed clock oscillation settling wait time 2 t hocowt2 ? ? t.b.d ms figure 5.6 high-speed clock power supply settling time t hocop ? ? t.b.d ms figure 5.7 pll input frequency f pllin 4 ? 12.5 mhz figure 5.8 pll circuit oscillation frequency f pll 50 ? 100 mhz pll clock oscillation settling time pll operation started after main clock oscillation has settled t pll1 ?? 500 s figure 5.9 pll clock oscillation settling wait time t pllwt1 1.5 ?? ms pll clock oscillation settling time pll operation started before main clock oscillation has settled t pll2 10 ?? ms figure 5.10 pll clock oscillation settling wait time t pllwt2 11 ?? ms sub-clock oscillator oscillation frequency f sub ? 32.768 ? khz sub-clock oscillati on settling time t subosc 2 ?? s figure 5.11 sub-clock oscillation settling wait time t suboscw t4 ?? s
r01ds0041ej0090 rev.0.90 page 94 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.1 bclk pin output , sdclk pin output timing figure 5.2 extal external clock input timing figure 5.3 main clock oscillation start timing figure 5.4 low-speed clock oscillation start timing t cf t ch t bcyc t cr t cl bclk pin output test conditions: voh = vcc 0.7, vol = v cc 0.3, ioh = -1.0 ma, iol = 1.0 ma, c = 30 pf t exh t excyc extal external clock input vcc 0.5 t exl t exr t exf main clock oscillator output mosccr.mostp t mainosc main clock t mainoscwt low-speed clock lococr.lcstp t locowt
r01ds0041ej0090 rev.0.90 page 95 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.5 high-speed clock oscillation start timing (after reset is canceled by setting the ofs1.hocoen bit to 0) figure 5.6 high-speed clock oscillation start timing (oscillation is st arted by setting the hococr.hcstp bit) figure 5.7 high-speed clock oscillator power supply control timing res# internal reset high-speed clock hococr.hcstp t hocowt1 t reswt res# internal reset high-speed clock hococr.hcstp t hocowt2 t reswt internal power supply for high-speed clock oscillator hocopcr.hocopcnt t hocop hococr.hcstp
r01ds0041ej0090 rev.0.90 page 96 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.8 pll circuit block figure 5.9 pll clock oscillation start timing (pll is operated after main clock oscillation has settled) figure 5.10 pll clock oscillation start timing (pll is operated be fore main clock oscillation has settled) phase comparator loop filter vco divider divider pll circuit f pllin f pll pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillator output pll circuit output t pll1 t pllwt1 mosccr.mostp pll circuit output pllcr2.pllen t pll2 t mainosc main clock oscillator output pll clock t pllwt2
r01ds0041ej0090 rev.0.90 page 97 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.11 pll clock oscillation start timing (pll is operated be fore main clock oscillation has settled) sub-clock oscillator output sosccr.sostp t subosc sub-clock t suboscwt
r01ds0041ej0090 rev.0.90 page 98 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.4.1 reset timing note: ? do not allow a reset by the signal on the res# pin during programming or erasure of the rom or e 2 data-flash memory or during blank checking of the e 2 data-flash memory. for details, see section 39.13, usage notes, in section 39, rom (flash memory for code storage). figure 5.12 reset input timing at power-on figure 5.13 reset input timing table 5.20 reset timing conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v t a = ?40 to +85c item symbol min. typ. max. unit test conditions res# pulse width power-on t reswp t.b.d ? ? ms figure 5.12 deep software standby mode t reswd t.b.d ? ? ms figure 5.13 software standby mode, low.speed operating mode 1, 2 t resws t. b . d ? ? m s other than above (except for programming or erasure of the rom or e 2 data-flash memory or blank checking of the e 2 data-flash memory) t resw t. b . d ? ? s wait time after res# cancellation t reswt t. b . d ? t. b . d t cyc figure 5.12 internal reset time (independent watchdog timer reset, watchdog timer reset, software reset) t resw2 t. b . d ? t. b . d t cyc vcc res# t reswp internal reset t reswt res# internal reset t reswt t reswd, t resws, t resw
r01ds0041ej0090 rev.0.90 page 99 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.4.2 timing of recovery from low power consumption modes note: ? the wait time varies depending on the state in which each oscillator was when the wait instruction was executed. the reco very time when multiple oscillators are operati ng is the same period as that when the os cillator, which takes the longest time for recovery among the operating oscillators, is operating alone. figure 5.14 software standby mode cancellation timing table 5.21 timing of recovery from low power consumption modes conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, iclk = up to 50 mhz, bclk = up to 25 mhz (bclk output = up to 12.5 mhz), t a = ?40 to +85c item symbol min. typ. max. unit test conditions recovery time after cancellation of software standby mode crystal resonator connected to main clock oscillator main clock oscillator operating t sbymc t.b.d ? ? ms figure 5.14 main clock oscillator and pll circuit operating t sbypc t. b . d ? ? m s external clock input to main clock oscillator main clock oscillator operating t sbyex t. b . d ? ? m s main clock oscillator and pll circuit operating t sbype t. b . d ? ? m s sub-clock oscillator operating t sbysc t. b . d ? ? s high-speed clock oscillator operating t sbyho ??t.b.dms low-speed clock oscillator or iwdt-specific low-speed clock oscillator operating t sbylo ??t.b.ds recovery time after cancellation of deep software standby mode t dsby ? ? t.b.d ms figure 5.15 wait time after cancellation of deep software standby mode t dsbywt t.b.d ? t.b.d t cyc oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbysc, t sbyho, t sbylo
r01ds0041ej0090 rev.0.90 page 100 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.15 deep software standby mode cancellation timing oscillator irq internal reset exceptional reset handling starts deep software standby mode deep software standby reset t dsby t dsbywt
r01ds0041ej0090 rev.0.90 page 101 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.4.3 control signal timing figure 5.16 nmi interrupt input timing figure 5.17 irq interrupt input timing table 5.22 control signal timing conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.62 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, iclk = up to 50 mhz, bclk = up to 25 mhz (bclk output = up to 12.5 mhz), t a = ?40 to +85c item symbol min. typ. max. unit test conditions nmi pulse width t nmiw t.b.d ? ? ns figure 5.16 irq pulse width t irqw t.b.d ? ? ns figure 5.17 nmi t nmiw irq t irqw
r01ds0041ej0090 rev.0.90 page 102 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.4.4 bus timing table 5.23 bus timing (1) conditions: avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, (bclk output = up to 12.5 mhz), t a = ?40 to +85c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. typ. max. unit address delay time t ad ? 60 ns figure 5.18 to figure 5.21 byte control delay time t bcd ?6 0n s cs# delay time t csd ?6 0n s rd# delay time t rsd ?6 0n s read data setup time t rds 40 ? ns read data hold time t rdh 0.0 ? ns wr# delay time t wrd ?6 0n s write data delay time t wdd ?6 0n s write data hold time t wdh 0.0 ? ns wait# setup time t wts 40 ? ns figure 5.22 wait# hold time t wth 0.0 ? ns table 5.24 bus timing (2) conditions: avcc0 = 1.8 to 2.7 v, vss = avss0 = vr efl = vrefl0 = 0 v (bclk output = up to 8 mhz), t a = ?40 to +85c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. typ. max. unit address delay time t ad ? 90 ns figure 5.18 to figure 5.21 byte control delay time t bcd ?9 0n s cs# delay time t csd ?9 0n s rd# delay time t rsd ?9 0n s read data setup time t rds 60 ? ns read data hold time t rdh 0.0 ? ns wr# delay time t wrd ?9 0n s write data delay time t wdd ?9 0n s write data hold time t wdh 0.0 ? ns wait# setup time t wts 60 ? ns figure 5.22 wait# hold time t wth 0.0 ? ns
r01ds0041ej0090 rev.0.90 page 103 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. table 5.25 bus timing (3) conditions: avcc0 = 1.62 to 1.8v, vss = avss0 = vrefl = vrefl0 = 0 v, (bclk output = to 6 mhz), t a = ?40 to +85c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. typ. max. unit address delay time t ad ? 125 ns figure 5.18 to figure 5.21 byte control delay time t bcd ? 125 ns cs# delay time t csd ? 125 ns rd# delay time t rsd ? 125 ns read data setup time t rds 85 ? ns read data hold time t rdh 0.0 ? ns wr# delay time t wrd ? 125 ns write data delay time t wdd ? 125 ns write data hold time t wdh 0.0 ? ns wait# setup time t wts 85 ? ns figure 5.22 wait# hold time t wth 0.0 ? ns
r01ds0041ej0090 rev.0.90 page 104 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.18 external bus timing/normal read cycle (bus clock synchronized) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 d15 to d0 (read) bus write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t ad t rdh t rds t ad t ad t bcd t w1 t w2 t end t n1 t h rdon:1 csrwait:2 csroff:1 cson:0
r01ds0041ej0090 rev.0.90 page 105 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.19 external bus timing/normal write cycle (bus clock synchronized) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd t ad t ad t ad t bcd d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w1 t w2 t end t n1 t h wron:1 wdon:1 [[ cswwait:2 cswoff:1 wdoff:1 [[ cson:0 note1. set the values of wdon and wdoff to 1 or greater.
r01ds0041ej0090 rev.0.90 page 106 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.20 external bus timing/page read cycle (bus clock synchronized) figure 5.21 external bus timing/page write cycle (bus clock synchronized) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 d15 to d0 (read) byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t rdh t rds t ad t bcd t w1 t w2 t end t pw1 t pw2 t ad t ad t rsd t rsd t rdh t rds t rsd t rsd t rdh t rds t end t pw1 t pw2 t end t n1 t h t ad t ad t ad t ad rdon:1 csrwait:2 csroff:1 t rsd t rsd t rdh t rds t ad t ad csprwait:2 t pw1 t pw2 t end rdon:1 csprwait:2 rdon:1 csprwait:2 rdon:1 cson:0 a23 to a1 cs3# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd t ad t bcd t w1 d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w2 t end t pw1 t pw2 t ad t ad t wrd t wrd t wdh t wdd t wrd t wrd t wdh t wdd t dw1 t end t pw1 t pw2 t end t n1 t h t dw1 t ad t ad t ad t ad wron:1 wdon:1 [[ cswwait:2 cspwwait:2 wdoff:1 [[ cspwwait:2 wdoff:1 [[ cswoff:1 wdoff:1 [[ cson:0 note1. set the values of wdon and wdoff to 1 or greater. wron:1 wdon:1 [[ wron:1 wdon:1 [[
r01ds0041ej0090 rev.0.90 page 107 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.22 external bus timing/external wait control t wts t wth t wts t wth csrwait:3 cswwait:3 bclk a23 to a0 cs3# to cs0# rd# (read) wr# (write) wait# t w1 t w2 (t end )t end t w3 t n1 t h external wait
r01ds0041ej0090 rev.0.90 page 108 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. table 5.26 bus timing (multiplexed bus) (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vref l = vrefl0 = 0 v, (bclk output = up to 12.5 mhz), t a = ?40 to +85c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. typ. max. unit address delay time t ad ? 60 ns figure 5.18 to figure 5.21 byte control delay time t bcd ?6 0n s cs# delay time t csd ?6 0n s rd# delay time t rsd ?6 0n s read data setup time t rds 40 ? ns read data hold time t rdh 0.0 ? ns wr# delay time t wrd ?6 0n s write data delay time t wdd ?6 0n s write data hold time t wdh 0.0 ? ns wait# setup time t wts 40 ? ns figure 5.22 wait# hold time t wth 0.0 ? ns ale output delay time (bclk standard) td(bclk-ale) taled ? 60 ns figure 5.23, figure 5.24 ale output delay time (address standard) td(ad-ale) t.b.d ? ns ale output hold time (address standard) th(ale-ad) t.b.d ? ns rd signal output delay time after address setup td(ad-rd) 0 ? ns wr signal output delay time after address setup td(ad-wr) 0 ? ns address output floating start time tdz(rd-ad) ? 60 ns
r01ds0041ej0090 rev.0.90 page 109 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. table 5.27 bus timing (multiplexed bus) (2) conditions: vcc = avcc0 = 1.8 to 2.7 v, vss = avss0 = vr efl = vrefl0 = 0 v, (bclk output = up to 8 mhz), t a = ?40 to +85c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. typ. max. unit address delay time t ad ? 90 ns figure 5.18 to figure 5.21 byte control delay time t bcd ?9 0n s cs# delay time t csd ?9 0n s rd# delay time t rsd ?9 0n s read data setup time t rds 60 ? ns read data hold time t rdh 0.0 ? ns wr# delay time t wrd ?9 0n s write data delay time t wdd ?9 0n s write data hold time t wdh 0.0 ? ns wait# setup time t wts 60 ? ns figure 5.22 wait# hold time t wth 0.0 ? ns ale output delay time (bclk standard) td(bclk-ale) taled ? 90 ns figure 5.23, figure 5.24 ale output delay time (address standard) td(ad-ale) t.b.d ? ns ale output hold time (address standard) th(ale-ad) t.b.d ? ns rd signal output delay time after address setup td(ad-rd) 0 ? ns wr signal output delay time after address setup td(ad-wr) 0 ? ns address output floating start time tdz(rd-ad) ? 90 ns
r01ds0041ej0090 rev.0.90 page 110 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. table 5.28 bus timing (multiplexed bus) (3) conditions: vcc = avcc0 = 1.62 to 1.8 v, vss = avss0 = vrefl = vrefl0 = 0v, (bclk output = up to 6 mhz), t a = ?40 to +85c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. typ. max. unit address delay time t ad ? 125 ns figure 5.18 to figure 5.21 byte control delay time t bcd ? 125 ns cs# delay time t csd ? 125 ns rd# delay time t rsd ? 125 ns read data setup time t rds 85 ? ns read data hold time t rdh 0.0 ? ns wr# delay time t wrd ? 125 ns write data delay time t wdd ? 125 ns write data hold time t wdh 0.0 ? ns wait# setup time t wts 85 ? ns figure 5.22 wait# hold time t wth 0.0 ? ns ale output delay time (bclk standard) td(bclk-ale) taled ? 125 ns figure 5.23, figure 5.24 ale output delay time (address standard) td(ad-ale) t.b.d ? ns ale output hold time (address standard) th(ale-ad) t.b.d ? ns rd signal output delay time after address setup td(ad-rd) 0 ? ns wr signal output delay time after address setup td(ad-wr) 0 ? ns address output floating start time tdz(rd-ad) ? 125 ns
r01ds0041ej0090 rev.0.90 page 111 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.23 example of operation in read access over the external bus (multiplexed) figure 5.24 example of operation in write access over the external bus (multiplexed) address/data bus data read (rd#) t ad bclk address address latch (ale) chip select (cs3# to cs0#) t w1 t wn t ad t ad t su(db-rd) 40ns(min) t end address cycle data cycle t aled t csd t csd t n1 t h 1 cycle fixed address cycle wait (await) t s(db-rd) 0ns(min) t rsd t rss t rsd t rss read-access cs extension cycle (csroff) t aled rd assert wait (rdon) normal read cycle wait (csrwait) cs assert wait (cson) a d t rdh t rds t d(ad-ale) t h(ale-ad) address/data bus data write (wr#) t ad bclk address address latch (ale) chip select (cs3# to cs0#) t w1 t ad t ad t end address cycle data cycle t csd t csd t n1 t h 1 cycle fixed t d(bclk-ale)= t aled address cycle wait (await) t rsd t rss t rsd t rss wr assert wait (wron) normal write cycle wait (csrwait) a d write data output wait (wdon) t d(bclk-ale)= t aled a read-access cs extension cycle (csroff)
r01ds0041ej0090 rev.0.90 page 112 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.4.5 timing of on-chi p peripheral modules note 1. t pcyc : pclk cycle note 2. set high driving ability for the output port pin to be used for the clock. note 3. set high driving ability for the output port pin to be used for the data. table 5.29 timing of on-chi p peripheral modules (1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.8 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. max. unit* 1 test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 5.25 mtu2a input capture input pulse width single-edge setting t ticw 1.5 ? t pcyc figure 5.26 both-edge setting 2.5 ? timer clock pulse width single-edge setting t tckwh, t tckwl 1.5 ? t pcyc figure 5.27 both-edge setting 2.5 ? phase counting mode 2.5 ? poe2 poe# input pulse width t poew 1.5 ? t pcyc figure 5.28 8-bit timer timer clock pulse width single-edge setting t tmcwh, t tmcwl 1.5 ? t pcyc figure 5.29 both-edge setting 2.5 ? sci input clock cycle asynchronous t scyc 4?t pcyc figure 5.30 clock synchronous 6? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ? t.b.d ns input clock fall time t sckf ? t.b.d ns output clock cycle asynchronous t scyc 16 ? t pcyc clock synchronous 4? output clock pulse width* 2 t sckw 0.4 0.6 t scyc output clock rise time* 2 t sckr ? t.b.d ns output clock fall time* 2 t sckf ? t.b.d ns transmit data delay time* 3 clock synchronous t txd ? t.b.d ns figure 5.31 receive data setup time clock synchronous t rxs t. b . d ? n s receive data hold time clock synchronous t rxh t. b . d ? n s a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 5.32
r01ds0041ej0090 rev.0.90 page 113 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. t pcyc : pclk cycle note 2. set high driving ability for the output port pin to be used for the clock. table 5.30 timing of on-chi p peripheral modules (2) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.8 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0v, t a = ?40 to +85c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. max. unit* 1 test conditions rspi rspck clock cycle master t spcyc 4 4096 t pcyc figure 5.33 slave 8 4096 rspck clock high pulse width* 2 master t spckwh t. b . d ? n s slave t.b.d ? rspck clock low pulse width* 2 master t spckwl t. b . d ? n s slave t.b.d ? rspck clock rise/fall time* 2 output t spckr, t spckf ? t.b.d ns input ? t.b.d s data input setup time master vcc ? 3.0 v t su t.b.d ? ns figure 5.34 to figure 5.37 vcc < 3.0 v t.b.d ? slave t.b.d ? data input hold time master t h t. b . d ? n s slave t.b.d ? ssl setup time master t lead 18t spcyc slave 4 ? t pcyc ssl hold time master t lag 18t spcyc slave 4 ? t pcyc data output delay time master t od ? t.b.d ns slave ? t.b.d data output hold time master t oh t. b . d ? n s slave t.b.d ? successive transmission delay time master t td t.b.d t.b.d ns slave t.b.d ? mosi and miso rise/ fall time output t dr, t df ? t.b.d ns input ? t.b.d s ssl rise/fall time output t sslr, t sslf ? t.b.d ns input ? t.b.d s slave access time t sa ?4t pcyc figure 5.36 and figure 5.37 slave output release time t rel ?3t pcyc
r01ds0041ej0090 rev.0.90 page 114 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. t pcyc : pclk cycle note 2. set high driving ability for the output port pin to be used for the clock. table 5.31 timing of on-chi p peripheral modules (3) conditions: vvcc = avcc0 = 1.62 to 5.5 v, vrefh = vrefh0 = 1.8 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0v, t a = ?40 to +85c output load conditions: v oh = vcc 0.5, v ol = vcc 0.5, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master)* 2 t spcyc 4 65536 t pcyc figure 5.33 sck clock cycle input (slave) 8 65536 sck clock high pulse width* 2 t spckwh 0.4 0.6 t spcyc sck clock low pulse width* 2 t spckwl 0.4 0.6 t spcyc sck clock rise/fall time* 2 t spckr, t spckf ? t.b.d ns data input setup time t su t.b.d ? ns figure 5.34 to figure 5.37 data input hold time t h t. b . d ? n s ss input setup time t lead 1?t spcyc ss input hold time t lag 1?t spcyc data output delay time t od ? t.b.d ns data output hold time t oh t. b . d ? n s data rise/fall time t dr, t df ? t.b.d ns ss input rise/fall time t sslr, t sslf ? t.b.d ns save access time t sa ?5t pcyc figure 5.36 and figure 5.37 slave output release time t rel ?5t pcyc
r01ds0041ej0090 rev.0.90 page 115 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. the value in parentheses is used when icmr3.nf[1:0] are set to 11b while a digital filter is enabled with icfer.nfe = 1. note 2. c b indicates the total capacity of the bus line. table 5.32 timing of on-chi p peripheral modules (4) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, pclkb = up to 32 mhz, t a = ?40 to +85c item symbol min.* 1, * 2 max. unit test conditions riic (standard-mode, smbus) icfer.fmpe = 0 scl input cycle time t scl 8(10) (1/pclk) + 1300 ? ns figure 5.38 scl input high pulse width t sclh 3(5) (1/pclk) + 300 ? ns scl input low pulse width t scll 5 (1/pclk) + 1000 ? ns scl, sda input rise time t sr ? 1000 ns scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 0 4 (1/pclk) ns sda input bus free time t buf 5 (1/pclk) + 1000 ? ns start condition input hold time t stah 3 (5) (1/pclk) + 300 ? ns restart condition input setup time t stas 5 (1/pclk) + 1000 ? ns stop condition input setup time t stos 3 (5) (1/pclk) + 300 ? ns data input setup time t sdas 250 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf riic (fast-mode) scl input cycle time t scl 8 (10) (1/pclk) + 600 ?ns scl input high pulse width t sclh 3 (5) (1/pclk) + 300 ? ns scl input low pulse width t scll 5 (1/pclk) + 300 ? ns scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 0 4 (1/pclk) ns sda input bus free time t buf 5 (1/pclk) + 300 ? ns start condition input hold time t stah 3 (5) (1/pclk) + 300 ? ns restart condition input setup time t stas 5 (1/pclk) + 300 ? ns stop condition input setup time t stos 3 (5) (1/pclk) + 300 ? ns data input setup time t sdas 100 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0041ej0090 rev.0.90 page 116 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. the value in parentheses is used when icmr3.nf[1:0] are set to 11b while a digital filter is enabled with icfer.nfe = 1. note 2. c b indicates the total capacity of the bus line. table 5.33 timing of on-chi p peripheral modules (5) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh=vrefh0 = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, pclkb = up to 32 mhz, t a = ?40 to +85c item symbol min.* 1, * 2 max. unit test conditions simple iic (standard-mode) sda input rise time t sr ? 1000 ns figure 5.38 sda input fall time t sf ? 300 ns sda input spike pulse removal time t sp 0 4 (1/pclk) ns data input setup time t sdas 250 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ?4 0 0p f simple iic (fast-mode) scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 0 4 (1/pclk) ns data input setup time t sdas 100 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ?4 0 0p f
r01ds0041ej0090 rev.0.90 page 117 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.25 i/o port input timing figure 5.26 mtu2a input/output timing figure 5.27 mtu2a clock input timing figure 5.28 poe# input timing port pclk t prw output compare output input capture input pclk t ticw mtclka to mtclkd pclk t tckwl t tckwh poen# input pclk t poew
r01ds0041ej0090 rev.0.90 page 118 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.29 8-bit timer clock input timing figure 5.30 sck clock input timing figure 5.31 sci input/output timing: clock synchronous mode figure 5.32 a/d converter external trigger input timing pclk tmci0 to tmci3 t tmcwl t tmcwh t sckw t sckr t sckf t scyc sckn (n = 0, 1, 5, 6, 8, 9, 12) t txd t rxs t rxh txdn rxdn sckn n = 0, 1, 5, 6, 8, 9, 12 adtrg0# pclk t trgw
r01ds0041ej0090 rev.0.90 page 119 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.33 rspi clock timing and simple spi clock timing figure 5.34 rspi timing (master, cpha = 0) and simple spi timing (master, cpha = 0) rspcka master select output rspcka slave select input t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 v cc, v ol = 0.3 v cc, v ih = 0.7 v cc, v il = 0.3 v cc t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out ssla3 to ssla0 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output
r01ds0041ej0090 rev.0.90 page 120 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.35 rspi timing (master, cpha = 1) and simple spi timing (master, cpha = 1) figure 5.36 rspi timing (slave, cpha = 0) and simple spi timing (slave, cpha = 0) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od ssla3 to ssla0 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input mosia input misoa output
r01ds0041ej0090 rev.0.90 page 121 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.37 rspi timing (slave, cpha = 1) and simple spi timing (slave, cpha = 1) figure 5.38 riic bus interface input/output timing and simple iic bus interface input/output timing t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input sda0 scl0 v ih v il t stah t sclh t scll p [[ s [[ t sf t sr t scl t sdah t sdas t stas t sp t stos p [ t buf note 1. s, p, and sr indicate the following conditions, respectively. s : start condition p : stop condition sr : restart condition test conditions v ih = vcc 0.7, v il = vcc 0.3 v ol = 0.6v, i ol = 6 ma (icfer.fmpe = 0) v ol = 0.4v, i ol = 15 ma (icfer.fmpe = 1) sr [[
r01ds0041ej0090 rev.0.90 page 122 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.5 a/d conversion characteristics note 1. the conversion time is the sum of the sampling time and t he comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the scanning is not supported. note 3. the value in parentheses indicates the sampling time. note 4. refer to the corresponding table for the types of channel. note 5. these are the characteristics when no pin function other than a/d converter input is in use. table 5.34 a/d conversion characteristics (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vref h = vrefh0 = (avcc0 - 0.9 v) to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, pclkd = 1 to 50 mhz, t a = ?40 to +85c item symbol min. typ. max. unit resolution 12 12 12 bit conversion time* 1 (operation at pclk = 50 mhz) permissible signal source impedance (max.) = 1 k ? t. b . d (t.b.d)* 3 ? ? s sampling in t.b.d states on a high-precision channel* 4 permissible signal source impedance (max.) = 1 k ? t. b . d (t.b.d)* 3 ? ? sampling in t.b.d states on a normal-precision channel* 4 permissible signal source impedance (max.) = 5 k ? t. b . d (t.b.d)* 3 ? ? sampling in t.b.d states on a high-precision channel* 4 permissible signal source impedance (max.) = 5 k ? t. b . d (t.b.d)* 3 ? ? sampling in t.b.d states on a normal-precision channel* 4 analog input capacitance ? ? t.b.d pf offset error ? t.b.d t.b.d lsb full-scale error ? t.b.d t.b.d lsb quantization error ? 0.5 lsb absolute accuracy ? t.b.d 8* 5 lsb high-precision channel ? t.b.d t.b.d* 5 lsb normal-precision channel dnl differential nonlinearity error ? 2.0 t.b.d lsb inl integral nonlinearity error ? 2.0 t.b.d lsb
r01ds0041ej0090 rev.0.90 page 123 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. the conversion time is the sum of the sampling time and t he comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the scanning is not supported. note 3. the value in parentheses indicates the sampling time. note 4. refer to the corresponding table for the types of channel. note 5. these are the characteristics when no pin function other than a/d converter input is in use. table 5.35 a/d conversion characteristics (2) conditions: vcc = avcc0 = 1.8 to 2.7 v, vref h = vrefh0 = (avcc0 .0.9 v) to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, pclkd = 1 to 32 mhz, t a = ?40 to +85c item symbol min. typ. max. unit resolution 12 12 12 bit conversion time* 1 (operation at pclk = 32 mhz) permissible signal source impedance (max.) = 1 k ? t. b . d (t.b.d)* 3 ? ? s sampling in t.b.d states on a high-precision channel* 4 permissible signal source impedance (max.) = 1 k ? t. b . d (t.b.d)* 3 ? ? sampling in t.b.d states on a normal-precision channel* 4 permissible signal source impedance (max.) = 5 k ? t. b . d (t.b.d)* 3 ? ? sampling in t.b.d states on a high-precision channel* 4 permissible signal source impedance (max.) = 5 k ? t. b . d (t.b.d)* 3 ? ? sampling in t.b.d states on a normal-precision channel* 4 analog input capacitance ? ? t.b.d pf offset error ? t.b.d t.b.d lsb full-scale error ? t.b.d t.b.d lsb quantization error ? 0.5 lsb absolute accuracy ? t.b.d 8* 5 lsb high-precision channel ? t.b.d t.b.d* 5 lsb normal-precision channel dnl differential nonlinearity error ? 2.0 t.b.d lsb inl integral nonlinearity error ? t.b.d t.b.d lsb
r01ds0041ej0090 rev.0.90 page 124 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. the conversion time is the sum of the sampling time and t he comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the scanning is not supported. note 3. the value in parentheses indicates the sampling time. note 4. refer to the corresponding table for the types of channel. note 5. these are the characteristics when no pin function other than a/d converter input is in use. table 5.36 a/d conversion characteristics (3) conditions: vcc = avcc0 = 1.62 to 1.8 v, vref h = vrefh0 = (avcc0 - t.b.d v) to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, pclkd = 1 to 16 mhz, t a = ?40 to +85c item symbol min. typ. max. unit resolution 12 12 12 bit conversion time* 1 (operation at pclk = 32 mhz) permissible signal source impedance (max.) = 1 k ? t. b . d (t.b.d)* 3 ? ? s sampling in t.b.d states on a high-precision channel* 4 permissible signal source impedance (max.) = 1 k ? t. b . d (t.b.d)* 3 ? ? sampling in t.b.d states on a normal-precision channel* 4 permissible signal source impedance (max.) = 5 k ? t. b . d (t.b.d)* 3 ? ? sampling in t.b.d states on a high-precision channel* 4 permissible signal source impedance (max.) = 5 k ? t. b . d (t.b.d)* 3 ? ? sampling in t.b.d states on a normal-precision channel* 4 analog input capacitance ? ? t.b.d pf offset error ? t.b.d t.b.d lsb full-scale error ? t.b.d t.b.d lsb quantization error ? 0.5 lsb absolute accuracy ? t.b.d 8* 5 lsb high-precision channel ? t.b.d t.b.d* 5 lsb normal-precision channel dnl differential nonlinearity error ? t.b.d t.b.d lsb inl integral nonlinearity error ? 2.0 t.b.d lsb table 5.37 channel classifi cation for a/d converter classification channel conditions high-precision channel an003 to an007 avcc0 = 1.62 to 5.5 v an000, an001, an002 avcc0 = 2.7 to 5.5 v, when the sample and hold circuit is in use. avcc0 = 1.62 to 5.5 v, when the sample and hold circuit is not in use. normal-precision channel an008 to an015 avcc0 = 1.62 to 5.5 v
r01ds0041ej0090 rev.0.90 page 125 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.6 d/a conversion characteristics 5.7 temperature sensor characteristics table 5.38 d/a conversion characteristics (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, pclkb = up to 32 mhz, t a = ?40 to +85c item min. typ. max. unit test conditions resolution 10 10 10 bit conversion time ? ? 3.0 s 20-pf capacitive load absolute accuracy ? t.b.d 4.0 lsb 4-m ? resistive load ??t . b . dl s b8 - m ? resistive load ro output resistance ? t.b.d ? k ? table 5.39 d/a conversion characteristics (2) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = 1.8 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, pclkb = up to 32 mhz, t a = ?40 to +85c item min. typ. max. unit test conditions resolution 10 10 10 bit conversion time ? ? 10.0 s 20-pf capacitive load absolute accuracy ? t.b.d 4.0 lsb 4-m ? resistive load ??t . b . dl s b8 - m ? resistive load ro output resistance ? t.b.d ? k ? table 5.40 temperature sensor characteristics conditions: vvcc = avcc0 = 1.8 to 5.5 v, vref h = vrefh0 = (avcc0 - 0.9 v) to avcc0, vss = avss0 = vrefl = vrefl0 = 0v, t a = ?40 to +85c item min. typ. max. unit test conditions relative accuracy D t.b.d D c temperature slope D t.b.d D mv/c output voltage (@25c) vcc = 3.6 to 5.5 v D t.b.d D v vcc = 2.7 to 3.6 v D t.b.d D vcc = 1.8 to 2.7 v D t.b.d D temperature sensor start time DD t.b.d s sampling time t.b.d 70 t.b.d s
r01ds0041ej0090 rev.0.90 page 126 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.8 comparator characteristics note 1. when the digital filter is disabled. table 5.41 comparator characteristics conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss 0 = vrefl = vrefl0 = 0v, pclkb = up to 32 mhz, t a = ?40 to +85c item symbol min. typ. max. unit test conditions comparator a external standard voltage input range lvref 1.4 D vcc v external comparison voltage (cmpa1, cmpa2) input range vi ?0.3 D vcc + 0.3 v internal standard voltage D t.b.d t.b.d t.b.d v offset DD 50 t.b.d mv comparator output delay time DD 3 D s at falling edge vi = lvref ? 100 mv D 1.5 D s at falling edge vi = lvref < 1 v D 2 D s at rising edge vi = lvref + 100 mv D 0.5 D s at rising edge vi > lvref + 1 v comparator operating currrent icmpa D 0.5 D a comparator b input standard voltage for cvrefb0, cvrefb1 vref 0 D vcc ? 1.4 v input standard voltage for cmpb0, cmpb1 vi ?0.3 D vcc + 0.3 v offset DDD 50 mv comparator output delay time td DD 1 s vi = vref + 100 mv comparator operating current icmpb D 75 150 a vcc = 5.0 v for total two channels
r01ds0041ej0090 rev.0.90 page 127 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.9 power-on reset circuit and voltage detecti on circuit characteristics table 5.42 power-on reset circuit and voltage detection circuit characteristics(1) conditions: vcc = avcc, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) low power consumption function disabled v por t.b.d t.b.d t.b.d v figure 5.39 low power consumption function enabled t.b.d t.b.d t.b.d voltage detection circuit (lvd0) v det0_0 t.b.d 1.72 t.b.d v figure 5.40 v det0_1 t.b.d 1.90 t.b.d v det0_2 t.b.d 2.85 t.b.d v det0_3 t.b.d 3.80 t.b.d voltage detection circuit (lvd1) v det1_0 t.b.d 4.15 t.b.d v figure 5.41 v det1_1 t.b.d 4.00 t.b.d v det1_2 t.b.d 3.85 t.b.d v det1_3 t.b.d 3.70 t.b.d v det1_4 t.b.d 3.55 t.b.d v det1_5 t.b.d 3.40 t.b.d v det1_6 t.b.d 3.25 t.b.d v det1_7 t.b.d 3.10 t.b.d v det1_8 t.b.d 2.95 t.b.d v det1_9 t.b.d 2.80 t.b.d v det1_a t.b.d 2.65 t.b.d v det1_b t.b.d 2.50 t.b.d v det1_c t.b.d 2.35 t.b.d v det1_d t.b.d 2.20 t.b.d v det1_e t.b.d 2.05 t.b.d v det1_f t.b.d 1.90 t.b.d
r01ds0041ej0090 rev.0.90 page 128 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. the minimum vcc down time indicates the time when vcc is below the minimum value of voltage detection levels v por , v det1, and v det2 for the por/ lvd. table 5.43 power-on reset circuit and voltage detection circuit characteristics (2) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss 0 = vrefl = vrefl0 = 0 v, pclkb = up to 32 mhz, t a = ?40 to +85c item symbol min. typ. max. unit test conditions voltage detection level voltage detection circuit (lvd2) v det2_0 t.b.d 4.15 t.b.d v figure 5.42 v det2_1 t.b.d 4.00 t.b.d v det2_2 t.b.d 3.85 t.b.d v det2_3 t.b.d 3.70 t.b.d v det2_4 t.b.d 3.55 t.b.d v det2_5 t.b.d 3.40 t.b.d v det2_6 t.b.d 3.25 t.b.d v det2_7 t.b.d 3.10 t.b.d v det2_8 t.b.d 2.95 t.b.d v det2_9 t.b.d 2.80 t.b.d v det2_a t.b.d 2.65 t.b.d v det2_b t.b.d 2.50 t.b.d v det2_c t.b.d 2.35 t.b.d v det2_d t.b.d 2.20 t.b.d v det2_e t.b.d 2.05 t.b.d v det2_f t.b.d 1.90 t.b.d v det2_ext t.b.d t.b.d t.b.d internal reset time power-on reset time t por ? t.b.d ? ms figure 5.39 lvd0 reset time t lvd0 ? t.b.d ? figure 5.40 lvd1 reset time t lvd1 ? t.b.d ? figure 5.41 lvd2 reset time t lvd2 ? t.b.d ? figure 5.42 minimum vcc down time* 1 t voff t.b.d ? ? s figure 5.39 response delay time t det ? ? 150 s figure 5.39 lvd operation stabilization time (after lvd is enabled) td (e-a) ? ? 100 s figure 5.41 hysteresis width (lvd1 and lvd2) v lvh ? 100 ? mv when selection is from among vdetx_0 to 5. ? 70 ? when selection is from among vdetx_6 to f.
r01ds0041ej0090 rev.0.90 page 129 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.39 power-on reset timing figure 5.40 voltage detection circuit timing (v det0 ) internal reset signal (active-low) vcc t voff t det t por t det t por t det v por t voff t lvd0 t det v det0 vcc internal reset signal (active-low)
r01ds0041ej0090 rev.0.90 page 130 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.41 voltage detection circuit timing (v det1 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1
r01ds0041ej0090 rev.0.90 page 131 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.42 voltage detection circuit timing (v det2 ) t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0041ej0090 rev.0.90 page 132 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.10 oscillation stop detection timing figure 5.43 oscillation stop detection timing table 5.44 oscillation stop detection circuit characteristics conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions detection time t dr ? ? t.b.d ms figure 5.43 t dr main clock or pll clock ostdsr.ostdf low-speed clock iclk
r01ds0041ej0090 rev.0.90 page 133 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.11 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogr am/ erase cycle is n times (n = 1000), erasing can be performed n ti mes for each block. for instance, when 128-byte programming is performed 16 times for different addresses in 2-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. this indicates the characteristic when reprogram is performed within the specification range including the minimum numbe r. table 5.45 rom (flash memory for code storage) characteristics (1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +85c item symbol min. typ. max. unit test conditions reprogramming/erasure cycle* 1 n pec 1000 ? ? times data hold time* 2 t drp 10 ? ? year fcu reset time t fcur t.b.d ? ? s table 5.46 rom (flash memory for code storage) characteristics (2) : high-speed operating mode, medium-speed operating mode a conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +85c item symbol min. typ. max. unit test conditions programming time 2 bytes t p2 ? 0.5 2.5 ms fclk = 32 mhz n pec ? 100 8 bytes t p8 ?0.52.5 128 bytes t p128 ?1.04.8 2 bytes t p2 ? t.b.d 3.0 ms fclk = 32 mhz n pec > 100 8 bytes t p8 ? t.b.d 3.2 128 bytes t p128 ? t.b.d 6.0 erasure time 2 kbytes t e2k ? 15 t.b.d ms fclk = 32 mhz n pec ? 100 2 kbytes t e2k ? t.b.d t.b.d ms fclk = 32 mhz n pec > 100 suspend delay time during programming (in programming/erasure priority mode) t spd ? ? 0.8 ms figure 5.44 fclk = 32 mhz first suspend delay time during programming (in suspend priority mode) t spsd1 ??120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??0.8ms suspend delay time during erasing (in programming/erasure priority mode) t sed ??0.8ms first suspend delay time during erasing (in suspend priority mode) t sesd1 ??120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??0.8ms
r01ds0041ej0090 rev.0.90 page 134 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. the operating frequency is 20 mhz (max.) when the voltage is in the range from 1.62 v to less than 1.8 v. table 5.47 rom (flash memory for code storage) characteristics (3) : medium-speed operating mode b conditions: vcc = avcc0 = 1.62 to 3.6 v, vrefh = vr efh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +85c item symbol min. typ. max. unit test conditions programming time* 1 2 bytes t p2 ? 0.8 3.5 ms fclk = 32 mhz n pec ? 100 8 bytes t p8 ?0.83.5 128 bytes t p128 ?1.68.3 2 bytes t p2 ? t.b.d 4.2 ms fclk = 32 mhz n pec > 100 8 bytes t p8 ? t.b.d 4.5 128 bytes t p128 ? t.b.d 10 erasure time 2 bytes t e2k ? 32 t.b.d ms fclk = 32 mhz n pec ? 100 2 bytes t e2k ? t.b.d t.b.d ms fclk = 32 mhz n pec > 100 suspend delay time during programming (in programming/erasure priority mode) t spd ? ? 1.6 ms figure 5.44 fclk = 32 mhz* 1 first suspend delay time during programming (in suspend priority mode) t spsd1 ??120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??1.6ms suspend delay time during erasing (in programming/erasure priority mode) t sed ??1.6ms first suspend delay time during erasing (in suspend priority mode) t sesd1 ??120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??1.6ms
r01ds0041ej0090 rev.0.90 page 135 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. 5.12 e 2 flash characteristics note 1. the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 100000 ), erasing can be performed n times for each block. for instance, when 8-byte programming is performed 16 times for different addresses in 128-byte block and then the entire block is eras ed, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (overwriting is prohibited). note 2. this indicates the characteristics when reprogram is performed within the s pecification range including the minimum numb er. table 5.48 e 2 data flash characteristics (1) item symbol min. typ. max. unit test conditions reprogramming/erasure cycle n dpec 100000 ? ? times data hold time t drp 10 ? ? year table 5.49 e 2 data flash characteristics (2) : high-speed operating mode, medium-speed operating mode a conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0v temperature range for the programming/erasure operation: t a = ?40 to +85c item symbol min. typ. max. unit test conditions programming time* 1 2 bytes t p2 ? 0.3 2.0 ms fclk = 32 mhz n pec ? 100 8 bytes t p8 ?0.42.2 2 bytes t p2 ? t.b.d 3.0 ms fclk = 32 mhz n pec > 100 8 bytes t p8 ? t.b.d 3.2 erasure time 128 bytes t e2k ? 4.5 t.b.d ms fclk = 32 mhz n pec ? 100 128 bytes t e2k ? t.b.d t.b.d ms fclk = 32 mhz n pec > 100 blank check time 2 bytes t bc2 ??35 s fclk = 32 mhz 2 kbytes t bc2k ??2.5ms suspend delay time during programming (in programming/erasure priority mode) t spd ? ? 0.8 ms figure 5.44 fclk = 32 mhz first suspend delay time during programming (in suspend priority mode) t spsd1 ??120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??0.8ms suspend delay time during erasing (in programming/erasure priority mode) t sed ??0.8ms first suspend delay time during erasing (in suspend priority mode) t sesd1 ??120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??0.8ms
r01ds0041ej0090 rev.0.90 page 136 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. note 1. the operating frequency is 20 mhz (max.) when the voltage is in the range from 1.62 v to less than 1.8 v. table 5.50 e 2 data flash characteristics (3) 3): medium-speed operating mode b conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0v temperature range for the programming/erasure operation: t a = ?40 to +85c item symbol min. typ. max. unit test conditions programming time* 1 2 bytes t p2 ? 0.6 2.8 ms fclk = 32 mhz n pec ? 100 8 bytes t p8 ?0.63.2 2 bytes t p2 ? t.b.d 4.2 ms fclk = 32 mhz n pec > 100 8 bytes t p8 ? t.b.d 4.5 erasure time 128 bytes t e2k ? 7 t.b.d ms fclk = 32 mhz n pec ? 100 128 bytes t e2k ? t.b.d t.b.d ms fclk = 32 mhz n pec > 100 blank check time 2 bytes t bc2 ? ? 40 fclk = 32 mhz* 1 2 kbytes t bc2k ??2.6 suspend delay time during programming (in programming/erasure priority mode) t spd ? ? 1.6 ms figure 5.44 fclk = 32 mhz* 1 first suspend delay time during programming (in suspend priority mode) t spsd1 ??120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??1.6ms suspend delay time during erasing (in programming/erasure priority mode) t sed ??1.6ms first suspend delay time during erasing (in suspend priority mode) t sesd1 ??12 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??1.6ms
r01ds0041ej0090 rev.0.90 page 137 of 144 aug 10, 2011 rx210 group 5. electrical characteristics under development preliminary document specifications in this document are tentative and subject to change. figure 5.44 flash memory pr ogram/erase suspend timing ? suspension during erasure fcu command fstatr0.frdy programming pulse ? suspension during programming program suspend ready not ready ready t spd programming fcu command fstatr0.frdy programming pulse ? suspension during programming ready not ready not ready t spsd1 fcu command fstatr0.frdy erasure pulse ? suspension during erasure erase suspend ready not ready ready t spd erasing in suspend priority mode in programming/erasure priority mode prog ram susp end res ume susp end res ume susp end res ume t spsd2 not ready t spsd1 programming programming programming application of the pulse stops application of the pulse continues fcu command erasure pulse ready not ready not ready t sesd1 erase susp end res ume susp end res ume susp end res ume t sesd2 not ready t sesd1 erasing erasing erasing application of the pulse stops application of the pulse continues fstatr0.frdy
r01ds0041ej0090 rev.0.90 page 138 of 144 aug 10, 2011 rx210 group appendix 1. package dimensions under development preliminary document specifications in this document are tentative and subject to change. appendix 1.pack age dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation. website. figure a 100-pin tflga (ptlg0100ja-a) p-tflga100-7x7-0.65 0.1g mass[typ.] 100f0g ptlg0100ja-a renesas code jeita package code previous code 0.15 v 0.20 w 0.08 0.485 0.435 0.385 max nom min dimension in millimeters symbol reference 7.0 d 7.0 e 1.05 a x 0.65 e 0.10 y b 1 b 0.31 0.35 0.39 0.575 z d z e 0.575 index mark b w s w a s a h g f e d c b 12345678 ys s a v 4 (laser mark) index mark j k 910 d e e e a z d z e b b b 1 ms ab ms ab
r01ds0041ej0090 rev.0.90 page 139 of 144 aug 10, 2011 rx210 group appendix 1. package dimensions under development preliminary document specifications in this document are tentative and subject to change. figure b 100-pin lqfp (plqp0100kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. y index mark x 12 5 26 50 51 75 76 100 f *1 *3 *2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e
r01ds0041ej0090 rev.0.90 page 140 of 144 aug 10, 2011 rx210 group appendix 1. package dimensions under development preliminary document specifications in this document are tentative and subject to change. figure c 80-pin lqfp (plqp0080kb-a) detail f c a l 1 l a 1 a 2 index mark *2 *1 *3 f 80 61 60 41 40 21 20 1 x z e z d e h e d h d e b p 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. previous code jeita package code renesas code plqp0080kb-a 80p6q-a mass[typ.] 0.5g p-lqfp80-12x12-0.50 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.1450.09 0.250.200.15 max nom min dimension in millimeters symbol reference 12.1 12.0 11.9 d 12.1 12.0 11.9 e 1.4 a 2 14.2 14.0 13.8 14.2 14.0 13.8 1.7 a 0.20.1 0 0.70.50.3 l x 10 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section c bp c 1 b 1 y s s
r01ds0041ej0090 rev.0.90 page 141 of 144 aug 10, 2011 rx210 group appendix 1. package dimensions under development preliminary document specifications in this document are tentative and subject to change. figure d 80-pin lqfp (plqp0080ja-a) l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e 0.65 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.27 0.32 0.37 0.09 0.145 0.20 0.13 0.825 0.825 0.30 0.125 1.0 p-lqfp80-14x14-0.65 0.6g mass[typ.] fp-80w / fp-80wv plqp0080ja-a renesas code jeita package code previous code include trim offset. dimension " *3" does not note) do not include mold flash. dimensions " *1" and "*2" 1. 2. c 1 c b p b 1 terminal cross section a 2 c l a 1 a l 1 detail f z e z d h e h d d e *2 *1 *3 f 80 61 60 41 40 21 20 1 index mark e b p m s ys
r01ds0041ej0090 rev.0.90 page 142 of 144 aug 10, 2011 rx210 group appendix 1. package dimensions under development preliminary document specifications in this document are tentative and subject to change. figure e 64-pin lqfp (plqp0064kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark *3 17 32 64 49 11 6 33 48 f *1 *2 x y b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.250.200.15 maxnommin dimension in millimeters symbol reference 10.110.0 9.9 d 10.110.0 9.9 e 1.4 a 2 12.212.0 11.8 12.212.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e
r01ds0041ej0090 rev.0.90 page 143 of 144 aug 10, 2011 rx210 group appendix 1. package dimensions under development preliminary document specifications in this document are tentative and subject to change. figure f 64-pin lqfp (plqp0064ga-a) terminal cross section b1 c1 bp c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. *3 11 6 17 32 33 48 49 64 f *1 *2 x index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code plqp0064ga-a 64p6u-a/ ? mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.420.370.32 maxnom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.2 0.1 0 0.70.50.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s
r01ds0041ej0090 rev.0.90 page 144 of 144 aug 10, 2011 rx210 group revision history under development preliminary document specifications in this document are tentative and subject to change. revision history rx210 group datasheet rev. date description page summary 0.50 apr.15, 2011 ? first edition, issued 0.90 aug.10, 2011 1. overview 4 table 1.1 outline of specifications: po wer supply voltage/ operating frequency, changed 17, 21, 24, 26 table 1.5 to table 1.8 list of pins and pin functions (pin name: lvcmp2 ? cmpa2), changed 2. cpu 51 table 2.14 instructions that are converted into multiple micro-operations (multiplier: 32 32 ? 64 bits), (memory source operand), added 4. i/o registers 63 table 5.1 list of i/o registers (addres s order), soscwtcr, locowtcr2, hocowtcr2, added 114 to 116 table 5.1 list of i/o registers (address order): interrupt source priority register, changed 5. electrical characteristics 85 to 137 newly added revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", and "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended where you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-owned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2011 renesas electronics corporation. all rights reserved. colophon 1.1

▲Up To Search▲

Price & Availability of R5F52108ADFP11

	To Download R5F52108ADFP11 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .